公开(公告)号：US20140127905A1

公开(公告)日：2014-05-08

申请号：US13670477

申请日：2012-11-07

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Lu-Ping Chiang

IPC: H01L21/04

CPC classification number: H01L21/04 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L23/528 ,  H01L29/06 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract translation: 提供了一种在基板中形成图案的方法，其中首先提供具有图案区域的基板。 在图案区域中的基板上形成多个条形掩模层。 条状掩模层中的至少两个相邻的条形掩模层中的每一个具有突出部分，并且突出部分彼此面对。 间隔件形成在条形掩模层的侧壁上，其中间隔物的厚度大于两个突出部分之间的距离的一半。 随后，去除条形掩模层。 通过使用间隔物作为掩模来进行蚀刻工艺，以在衬底中形成沟槽。 此后，沟槽被填充材料。

公开(公告)号：US08659950B1

公开(公告)日：2014-02-25

申请号：US13902863

申请日：2013-05-27

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Lu-Ping Chiang

IPC: G11C16/06

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE′ is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.

Abstract translation: 提供了利用小型化的感测电路执行高速读取的半导体存储器件。 当选择偶数位线时，来自虚拟电位VPRE'的预充电电压被提供给奇数位线，预充电电压从源电压提供单元230提供给共享奇数源极线SL_o，地 电源电压提供单元230提供给偶数源极线SL_e。

公开(公告)号：US20190319037A1

公开(公告)日：2019-10-17

申请号：US16215666

申请日：2018-12-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L27/11531

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

公开(公告)号：US10381449B2

公开(公告)日：2019-08-13

申请号：US15867736

申请日：2018-01-11

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsien Liu ,  Chun-Hsu Chen ,  Lu-Ping Chiang

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L21/311 ,  H01L29/49 ,  H01L27/11521 ,  H01L21/762

Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

公开(公告)号：US08697538B1

公开(公告)日：2014-04-15

申请号：US13670477

申请日：2012-11-07

Applicant: Winbond Electronics Corp.

Inventor： Lu-Ping Chiang

IPC: H01L21/76 ,  H01L21/44 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/04 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L23/528 ,  H01L29/06 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract translation: 提供了一种在基板中形成图案的方法，其中首先提供具有图案区域的基板。 在图案区域中的基板上形成多个条形掩模层。 条状掩模层中的至少两个相邻的条形掩模层中的每一个具有突出部分，并且突出部分彼此面对。 间隔件形成在条形掩模层的侧壁上，其中间隔物的厚度大于两个突出部分之间的距离的一半。 随后，去除条形掩模层。 通过使用间隔物作为掩模来进行蚀刻工艺，以在衬底中形成沟槽。 此后，沟槽被填充材料。

公开(公告)号：US20140063970A1

公开(公告)日：2014-03-06

申请号：US13902863

申请日：2013-05-27

Applicant: Winbond Electronics Corp.

Inventor： Masaru Yano ,  Lu-Ping Chiang

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE′ is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.

Abstract translation: 提供了利用小型化的感测电路执行高速读取的半导体存储器件。 当选择偶数位线时，来自虚拟电位VPRE'的预充电电压被提供给奇数位线，预充电电压从源电压提供单元230提供给共享奇数源极线SL_o，地 电源电压提供单元230提供给偶数源极线SL_e。