公开(公告)号：US06839397B2

公开(公告)日：2005-01-04

申请号：US09907784

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： G11C29/14 ,  G06M3/00

CPC分类号： G11C29/14

摘要： A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

摘要翻译： 描述用于产生用于测试高频同步数字电路，特别是存储器芯片的控制信号的电路配置。 以对应于要测试的数字电路的高时钟频率的时钟频率计时的p级移位寄存器连接到其并行加载输入p逻辑门，逻辑门逻辑地将静态控制字与动态n位置测试 字。 组合的逻辑值以低频加载时钟速率被加载到移位寄存器中，使得其值取决于在后者的时钟频率的每个时钟周期中加载到移位寄存器中的信息的控制信号 在移位寄存器的串行输出。

公开(公告)号：US06871306B2

公开(公告)日：2005-03-22

申请号：US09907692

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C29/56

摘要： A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

摘要翻译： 一种用于读取和检查从要测试的存储器模块读出的数据响应的时间位置的方法和装置，特别是在DDR操作中操作的DRAM存储器。 在测试接收机中，要测试的存储器模块的数据响应被锁存到具有被延迟的数据选通响应信号的数据锁存器中。 产生对称时钟信号作为校准信号。 校准信号用于校准相对于数据响应的延迟数据选通响应信号的时间位置。 延迟的数据选通响应信号用于锁存数据响应。 延迟时间在校准操作期间被编程到延迟器件中，并且还提供测量数据选通响应信号（DQS）和数据响应之间的精确时间关系。

公开(公告)号：US06853206B2

公开(公告)日：2005-02-08

申请号：US10736356

申请日：2003-12-15

申请人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter P{hacek over (o)}chmüller ,  Jürgen Weidenhöfer

发明人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter P{hacek over (o)}chmüller ,  Jürgen Weidenhöfer

IPC分类号： G01R31/3185 ,  G01R31/319 ,  G11C29/00 ,  G11C29/48 ,  G01R31/02 ,  G01R31/28

CPC分类号： G01R31/319 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G11C29/006 ,  G11C29/48

摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

摘要翻译： 用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。 测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块 。 有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。 在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

公开(公告)号：US06762611B2

公开(公告)日：2004-07-13

申请号：US10010504

申请日：2001-12-05

申请人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter Pöchmüller ,  Jürgen Weidenhöfer

发明人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter Pöchmüller ,  Jürgen Weidenhöfer

IPC分类号： G01R1073

CPC分类号： G01R31/319 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G11C29/006 ,  G11C29/48

摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

摘要翻译： 用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。 测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块 。 有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。 在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

公开(公告)号：US06515319B2

公开(公告)日：2003-02-04

申请号：US09861431

申请日：2001-05-18

申请人： Dietrich Widmann ,  Armin Wieder ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pochmüller ,  Michael Schittenhelm

发明人： Dietrich Widmann ,  Armin Wieder ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pochmüller ,  Michael Schittenhelm

IPC分类号： H01L31119

CPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/66787

摘要： An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

公开(公告)号：US06910161B2

公开(公告)日：2005-06-21

申请号：US10016863

申请日：2001-12-14

申请人： Justus Kuhn ,  Peter Weitz

发明人： Justus Kuhn ,  Peter Weitz

IPC分类号： G11C29/00 ,  G11C16/06

CPC分类号： G11C29/72 ,  G11C29/814

摘要： A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word lines or bit lines which are to be completely repaired, these addresses are referred to as second fault addresses. If the first fault address corresponds to the second fault address, the first fault address is deleted and not further processed. In a second comparison, it is determined, by reference to the number of non-deleted first fault addresses, whether an address of a word line or bit line is used as a new second fault address for the first comparison method. The number of addresses of faulty memory cells are thus reduced.

摘要翻译： 用于减少故障存储器单元的地址的方法和设备将故障存储器单元的地址作为第一故障地址与待完全修复的字线或位线的地址进行比较，这些地址被称为第二故障地址。 如果第一个故障地址对应于第二个故障地址，则第一个故障地址被删除，而不进一步处理。 在第二比较中，通过参照未删除的第一故障地址的数量，确定字线或位线的地址是否用作第一比较方法的新的第二故障地址。 因此，故障存储器单元的地址数量减少。

公开(公告)号：US20060064620A1

公开(公告)日：2006-03-23

申请号：US11227714

申请日：2005-09-15

申请人： Justus Kuhn ,  Wolfgang Spirkl

发明人： Justus Kuhn ,  Wolfgang Spirkl

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/028 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50012

摘要： The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting data stored in the semiconductor memory apparatus, at least one phase adjustment device which is designed for approximately adjusting a phase of the data read clock signal on the basis of a phase of the external clock signal at least one phase difference test device which is designed for approximately detecting a phase difference between the phase of the data read clock signal and the phase of the external clock signal and for outputting a test result on the basis of the detected phase difference.

摘要翻译： 本发明涉及具有用于输入外部时钟信号的至少一个时钟输入触点的半导体存储装置，至少一个时钟输出触点，用于输出用于读取存储在半导体存储装置中的数据的数据读取时钟信号，至少一个数据触点 用于输出存储在所述半导体存储装置中的数据，所述至少一个相位调整装置被设计为基于所述外部时钟信号的相位近似地调整所述数据读取时钟信号的相位，所述至少一个相位差测试装置是 设计用于近似地检测数据读时钟信号的相位与外部时钟信号的相位之间的相位差，并且用于基于检测到的相位差输出测试结果。

公开(公告)号：US07043653B2

公开(公告)日：2006-05-09

申请号：US10215228

申请日：2002-08-08

申请人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

发明人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

摘要翻译： 将接收信号的逻辑/存储器组件的内部时钟信号作为参考时钟发送到发送逻辑/存储器组件。 借助于参考时钟，产生发送逻辑/存储器部件的输出单元的传输时钟，使得发送的信号与该部件的内部时钟信号同步到达接收部件的接收单元。

公开(公告)号：US06954871B2

公开(公告)日：2005-10-11

申请号：US10147545

申请日：2002-05-16

申请人： Justus Kuhn

发明人： Justus Kuhn

IPC分类号： G06F13/16 ,  G06F1/04

CPC分类号： G06F13/161

摘要： In a fast synchronously controlled computer system, data signals are called from various memory banks, and this can result in propagation times of different lengths for the data signals, depending on the physical distance from the controller. Therefore, the data signals from a memory bank closer to the controller enter the controller earlier than in the case of a further removed one. To cure this problem, the controller sends an additional read signal that is also transmitted bi-directionally, first to the furthest removed data buffer of an associated memory bank and then to the closer data buffers of the corresponding memory banks. As a result, a sum of signal propagation times of the read signal from the controller to the respective memory bank and that of the read data from the memory bank to the controller is always of the same length, irrespective of the position of the memory bank.

摘要翻译： 在快速同步控制的计算机系统中，数据信号被从各种存储体调用，这可能导致数据信号的不同长度的传播时间，这取决于与控制器的物理距离。 因此，更靠近控制器的存储体的数据信号比进一步去除的情况更早地进入控制器。 为了解决这个问题，控制器发送一个另外的读取信号，它也是双向传输的，首先是相关存储体的最远去除的数据缓冲器，然后到相应存储体的更靠近的数据缓冲器。 结果，与存储体的位置无关地，从控制器到各个存储体的读信号和从存储体到控制器的读数据的信号传播时间的总和总是相同的长度 。

公开(公告)号：US07307895B2

公开(公告)日：2007-12-11

申请号：US11227714

申请日：2005-09-15

申请人： Justus Kuhn ,  Wolfgang Spirkl

发明人： Justus Kuhn ,  Wolfgang Spirkl

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50012

摘要： The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting data stored in the semiconductor memory apparatus, at least one phase adjustment device which is designed for approximately adjusting a phase of the data read clock signal on the basis of a phase of the external clock signal at least one phase difference test device which is designed for approximately detecting a phase difference between the phase of the data read clock signal and the phase of the external clock signal and for outputting a test result on the basis of the detected phase difference.

摘要翻译： 本发明涉及具有用于输入外部时钟信号的至少一个时钟输入触点的半导体存储装置，至少一个时钟输出触点，用于输出用于读取存储在半导体存储装置中的数据的数据读取时钟信号，至少一个数据触点 用于输出存储在所述半导体存储装置中的数据，所述至少一个相位调整装置被设计为基于所述外部时钟信号的相位近似地调整所述数据读取时钟信号的相位，所述至少一个相位差测试装置是 设计用于近似地检测数据读时钟信号的相位与外部时钟信号的相位之间的相位差，并且用于基于检测到的相位差输出测试结果。