公开(公告)号：US4581319A

公开(公告)日：1986-04-08

申请号：US616113

申请日：1984-06-01

申请人： Armin Wieder ,  Hans-Christian Schaber ,  Siegfried Schwarzl

发明人： Armin Wieder ,  Hans-Christian Schaber ,  Siegfried Schwarzl

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L29/732 ,  G03C5/00 ,  B44C1/22

CPC分类号： H01L29/66295 ,  H01L21/0337

摘要： A method for the manufacture of bipolar transistor structures with self-adjusted emitter and base regions wherein the emitter and base regions are generated by an out-diffusion from doped polysilicon layers. Dry etching processes which produce vertical etching profiles are employed for structuring the SiO.sub.2 and polysilicon layers. The employment of additional oxidation processes for broadening the lateral edge insulation (see arrow 9) during the manufacture of the bipolar transistor structures enables self-adjusted emitter-base structures with high reproducibility in addition to advantages with respect to the electrical parameters. The method is employed for the manufacture of VLSI circuits in bipolar technology.

摘要翻译： 一种用于制造具有自调节发射极和基极区域的双极晶体管结构的方法，其中发射极和基极区域由掺杂多晶硅层的向外扩散产生。 使用产生垂直蚀刻轮廓的干蚀刻工艺来构造SiO 2和多晶硅层。 在双极晶体管结构的制造期间，采用额外的氧化工艺来扩展侧边缘绝缘（参见箭头9），除了电参数的优点之外，还能实现具有高再现性的自调节发射极 - 基极结构。 该方法用于制造双极性技术中的VLSI电路。

公开(公告)号：US4336604A

公开(公告)日：1982-06-22

申请号：US169449

申请日：1980-07-16

申请人： Armin Wieder

发明人： Armin Wieder

IPC分类号： G11C11/412 ,  G11C11/35 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/10 ,  H01L27/11 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L27/1112 ,  G11C11/35

摘要： A monolithic static memory cell has a region of a first conductivity type extending from the upper surface of a semiconductor layer of a second conductivity type carried on a semiconductor body of the first conductivity type and connected to a first drive line. A first zone of the semiconductor layer adjacent the region is covered by a gate connected to a second drive line and separated from the semiconductor layer by a gate insulator. A second zone adjacent the first zone is covered by a conductive coating connected to a supply terminal, the conductive coating being separated from the surface of the semiconductor layer by a thin electrically insulating layer which admits a tunnel current between the surface of the semiconductor layer and the conductive coating.

摘要翻译： 单片静电存储单元具有从第一导电类型的半导体本体上承载的第二导电类型的半导体层的上表面延伸并连接到第一驱动线的第一导电类型的区域。 邻近该区域的半导体层的第一区被连接到第二驱动线的栅极覆盖，并通过栅极绝缘体与半导体层分离。 邻近第一区的第二区被连接到供电端的导电涂层覆盖，导电涂层通过薄的电绝缘层与半导体层的表面分开，该绝缘层允许在半导体层的表面和 导电涂层。

公开(公告)号：US4300279A

公开(公告)日：1981-11-17

申请号：US169528

申请日：1980-07-16

申请人： Armin Wieder

发明人： Armin Wieder

IPC分类号： H01L27/04 ,  G11C11/35 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L21/90

CPC分类号： H01L27/1112 ,  G11C11/35

摘要： Production of high bit density memory cells using six selective, vertically aligned, reactive plasma etching steps. A gate oxide layer is applied to the boundary surface of the semiconductor layer and has a polysilicon layer which is highly doped and covered with a first intermediate oxide layer. A drive line and the gate are first formed. Sections of the drive line at the ends thereof are removed by isotropic etching and the resulting recesses are filled in a thermal oxidation step. The portion of the gate oxide layer adjacent the structured parts is removed by a second etching step. A second polysilicon layer is deposited, highly doped and covered with a second intermediate oxide layer. Another drive line having a part contacting a doped region in the semiconductor layer, the region being formed by ion implantation, is structured by a third etching step. A recess is then formed by a fourth etching step and an isotropic etching step is performed to remove those parts of the drive line which extend to the last-mentioned recess. A fifth etching step is performed for removing the oxide layer covering the boundary surface of the semiconductor layer within the recess. A third, silicon layer is deposited and covered with a third intermediate oxide layer. Another recess is formed in the third intermediate oxide layer above the recess provided by the fourth etching in a sixth etching step. A conductive coating is then applied to the third polysilicon layer and is provided with an electrical terminal.

摘要翻译： 使用六个选择性，垂直排列的反应等离子体蚀刻步骤生产高位密度存储单元。 栅极氧化物层被施加到半导体层的边界表面，并且具有高掺杂并被第一中间氧化物层覆盖的多晶硅层。 驱动线和闸门首先形成。 通过各向同性蚀刻除去其端部的驱动线的部分，并将所得的凹部填充在热氧化步骤中。 通过第二蚀刻步骤去除与结构化部分相邻的栅氧化层的部分。 沉积第二多晶硅层，高度掺杂并用第二中间氧化物层覆盖。 具有与半导体层中的掺杂区域接触的部分的另一驱动线，该离子注入形成的区域通过第三蚀刻步骤构成。 然后通过第四蚀刻步骤形成凹部，并且执行各向同性蚀刻步骤以去除延伸到最后提到的凹部的驱动线的那些部分。 执行第五蚀刻步骤，以去除覆盖在凹部内的半导体层的边界表面的氧化物层。 第三个硅层被沉积并被第三中间氧化物层覆盖。 在第六蚀刻步骤中由第四蚀刻提供的凹部上方的第三中间氧化物层中形成另一凹部。 然后将导电涂层施加到第三多晶硅层并且设置有电端子。

公开(公告)号：US06515319B2

公开(公告)日：2003-02-04

申请号：US09861431

申请日：2001-05-18

申请人： Dietrich Widmann ,  Armin Wieder ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pochmüller ,  Michael Schittenhelm

发明人： Dietrich Widmann ,  Armin Wieder ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pochmüller ,  Michael Schittenhelm

IPC分类号： H01L31119

CPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/66787

摘要： An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

公开(公告)号：US4823180A

公开(公告)日：1989-04-18

申请号：US437302

申请日：1982-10-28

申请人： Armin Wieder ,  Lothar Risch

发明人： Armin Wieder ,  Lothar Risch

IPC分类号： H01L31/10 ,  H01L29/04 ,  H01L31/113 ,  H01L27/14

CPC分类号： H01L29/04 ,  H01L31/1136

摘要： A photo-transistor in MOS thin-film technology operable with alternating voltages is comprised of a semiconductor body (3) composed of polycrystalline silicon having source (4) and drain (5) zones therein spaced apart by an undoped channel region (13) and having a gate electrode (1, 10) separated from the semiconductor body (3) by a SiO.sub.2 layer (2) produced by thermal oxidation. These phototransistors are easily and reproducably produced and are characterized by low threshold voltages and a good transistor characteristic curve. Thus, these photo-transistors are well suited for use as sensor elements, opto-couplers, time-delay elements and as photo-transistors in VLSI circuits.

摘要翻译： 可以用交流电压工作的MOS薄膜技术的光电晶体管由半导体本体（3）组成，半导体本体（3）由多晶硅构成，多晶硅具有由未掺杂沟道区（13）间隔的源极（4）和漏极（5） 具有通过由热氧化产生的SiO 2层（2）与半导体本体（3）分离的栅电极（1,10）。 这些光电晶体管容易且可再生产，其特征在于低阈值电压和良好的晶体管特性曲线。 因此，这些光电晶体管非常适合用作VLSI电路中的传感器元件，光耦合器，延时元件和光电晶体管。

公开(公告)号：US4737472A

公开(公告)日：1988-04-12

申请号：US931640

申请日：1986-11-17

申请人： Hans-Christian Schaber ,  Armin Wieder ,  Johannes Bieger

发明人： Hans-Christian Schaber ,  Armin Wieder ,  Johannes Bieger

IPC分类号： H01L29/78 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/00 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L21/8249 ,  Y10S148/009 ,  Y10S148/124

摘要： A process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones. The n-zones form the collectors of the transistors and are modified according to conventional technology by additional process steps such that bipolar transistors are formed which are self-aligning both between the emitter and the base and also between the base and collector with extremely low-ohmic base terminals consisting of polysilicon and a silicide. Storage capacitances can also additionally be integrated into the structure. The use of the base terminals thus produced permits very small lateral emitter-collector distances. The combination of dynamic CMOS memory cells with fast bipolar transistors is made possible by the integration of the storage capacitances. The process is used for the production of VLSI circuits of high switching speeds.

摘要翻译： 在公共硅衬底上同时生产自对准双极晶体管和互补MOS晶体管的方法，其中在p掺杂衬底中产生n掺杂区并且将绝缘npn双极晶体管形成为n掺杂区。 n区形成晶体管的集电极，并根据常规技术通过附加的工艺步骤进行修改，使得形成双极晶体管，其在发射极和基极之间以及在基极和集电极之间自对准， 由多晶硅和硅化物构成的欧姆基极。 存储电容也可以另外集成到结构中。 使用如此制造的基座端子允许非常小的横向发射极 - 集电极距离。 动态CMOS存储器单元与快速双极晶体管的组合通过存储电容的集成成为可能。 该过程用于生产高切换速度的VLSI电路。