公开(公告)号：US20240403253A1

公开(公告)日：2024-12-05

申请号：US18204246

申请日：2023-05-31

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Krishnan SRINIVASAN ,  Brian C. GAIDE ,  Ahmad R. ANSARI ,  Sagheer AHMAD

IPC: G06F13/40 ,  G06F13/42

Abstract: Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options

公开(公告)号：US20240281537A1

公开(公告)日：2024-08-22

申请号：US18111808

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  James D. WESSELKAMPER ,  James ANDERSON ,  Nader SHARIFI ,  Ahmad R. ANSARI ,  Sagheer AHMAD ,  Brian C. GAIDE

IPC: G06F21/57 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30

CPC classification number: G06F21/575 ,  H04L9/0618 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/14 ,  H04L9/30 ,  G06F2221/034

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

公开(公告)号：US20240103562A1

公开(公告)日：2024-03-28

申请号：US18521301

申请日：2023-11-28

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE

IPC: G06F1/10 ,  H01L23/00

CPC classification number: G06F1/10 ,  H01L24/02 ,  H01L2224/08145

Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

公开(公告)号：US20240096405A1

公开(公告)日：2024-03-21

申请号：US17950022

申请日：2022-09-21

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4093

Abstract: A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.

公开(公告)号：US20250004983A1

公开(公告)日：2025-01-02

申请号：US18215668

申请日：2023-06-28

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sneha Bhalchandra DATE ,  Juan J. NOGUERA SERRA

IPC: G06F15/80

Abstract: Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

公开(公告)号：US20240387388A1

公开(公告)日：2024-11-21

申请号：US18199334

申请日：2023-05-18

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Aman GUPTA

IPC: H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

公开(公告)号：US20240385642A1

公开(公告)日：2024-11-21

申请号：US18199838

申请日：2023-05-19

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE

IPC: G06F1/10

Abstract: An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.

公开(公告)号：US20240330222A1

公开(公告)日：2024-10-03

申请号：US18128936

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE

IPC: G06F13/40 ,  H01L25/065 ,  H10B80/00

CPC classification number: G06F13/4027 ,  H01L25/0657 ,  H10B80/00 ,  H01L2225/06565

Abstract: A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.

公开(公告)号：US20230268280A1

公开(公告)日：2023-08-24

申请号：US17677899

申请日：2022-02-22

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Brian C. GAIDE

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L23/49822 ,  H01L24/06 ,  H01L23/49838 ,  H01L25/18 ,  H01L2224/0612

Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.