公开(公告)号：US11599498B1

公开(公告)日：2023-03-07

申请号：US17068697

申请日：2020-10-12

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran Hk Bilski

IPC: G06F9/00 ,  G06F15/177 ,  G06F15/80 ,  G06F15/173 ,  G06F9/4401

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11573726B1

公开(公告)日：2023-02-07

申请号：US17097917

申请日：2020-11-13

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick ,  Philip B. James-Roxby

IPC: G06F3/06 ,  G06F15/173 ,  G06F15/78

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

公开(公告)号：US11323391B1

公开(公告)日：2022-05-03

申请号：US16833029

申请日：2020-03-27

Applicant: XILINX, INC.

Inventor： Peter McColgan ,  David Clarke ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Tim Tuan

IPC: H04L12/935 ,  G06F13/28 ,  H04L49/00

Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.

公开(公告)号：US11061673B1

公开(公告)日：2021-07-13

申请号：US15944393

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Baris Ozgul ,  Jan Langer ,  Juan J. Noguera Serra ,  Goran H. K. Bilski ,  Richard L. Walke

IPC: G06F9/30 ,  G06F17/16

Abstract: An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.

公开(公告)号：US11016822B1

公开(公告)日：2021-05-25

申请号：US15944578

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H. K. Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke

IPC: G06F9/50 ,  G06F9/48

Abstract: Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.

公开(公告)号：US10990552B1

公开(公告)日：2021-04-27

申请号：US15944464

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran Hk Bilski ,  Peter McColgan ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/40 ,  G06F13/42

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.

公开(公告)号：US12105667B2

公开(公告)日：2024-10-01

申请号：US18114850

申请日：2023-02-27

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran H. k. Bilski

IPC: G06F9/24 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F1/24 ,  G06F9/4401

CPC classification number: G06F15/177 ,  G06F15/17306 ,  G06F15/80 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4411

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US20230053537A1

公开(公告)日：2023-02-23

申请号：US17819879

申请日：2022-08-15

Applicant: Xilinx, Inc.

Inventor： Baris Ozgul ,  David Clarke ,  Peter McColgan ,  Stephan Munz ,  Dylan Stuart ,  Pedro Miguel Parola Duarte ,  Juan J. Noguera Serra

IPC: G06F13/16 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063

Abstract: Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a different mode of data movement in the data processing array via the stream channels. For each overlay implemented, a workload is performed by moving data to the plurality of compute tiles based on the respective mode of data movement.

公开(公告)号：US11567881B1

公开(公告)日：2023-01-31

申请号：US15944602

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H. K. Bilski ,  David Clarke ,  Baris Ozgul ,  Jan Langer ,  Juan J. Noguera Serra

IPC: G06F13/10 ,  G06F13/16

Abstract: A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.

公开(公告)号：US11379389B1

公开(公告)日：2022-07-05

申请号：US15944179

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/16 ,  G06F12/084 ,  G06F9/54 ,  G11C8/16 ,  G06F15/167

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.