公开(公告)号：US09341668B1

公开(公告)日：2016-05-17

申请号：US14242760

申请日：2014-04-01

Applicant: Xilinx, Inc.

Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Glenn O'Rourke ,  Inderjit Singh ,  Eric J. Thorne ,  David E. Schweigler

IPC: G01R31/00 ,  G01R31/26 ,  G01R1/04

CPC classification number: G01R31/2889 ,  G01R1/0416

Abstract: A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

Abstract translation: 可测试电路装置包括集成电路（IC）封装。 IC封装包括封装衬底，直接安装在具有级别1互连的封装衬底上的插入件以及直接安装在具有0级互连的插入器上的至少一个IC管芯。 IC封装的封装基板直接安装在具有2级互连的焊接球栅格阵列的连接器板上。 0级，1级和2级互连包括各自的功率，配置和测试互连。 连接器板的电源，配置和测试端子耦合到2级互连的电源，配置和测试互连。

公开(公告)号：US11075117B2

公开(公告)日：2021-07-27

申请号：US15904764

申请日：2018-02-26

Applicant: Xilinx, Inc.

Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Inderjit Singh

IPC: H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/263 ,  H01L21/683 ,  H01L21/3065 ,  H01L23/00 ,  H01L23/31

Abstract: Techniques for singulating dies from a respective workpiece and for incorporating one or more singulated die into a stacked device structure are described herein. In some examples, singulating a die from a workpiece includes chemically etching the workpiece in a scribe line. In some examples, singulating a die from a workpiece includes mechanically dicing the workpiece in a scribe line and forming a liner along a sidewall of the die. The die can be incorporated into a stacked device structure. The die can be attached to a substrate along with another die that is attached to the substrate. An encapsulant can be between each die and the substrate and laterally between the dies.

公开(公告)号：US10438863B1

公开(公告)日：2019-10-08

申请号：US16138671

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Ronilo Boja ,  Inderjit Singh

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/488

Abstract: A chip package assembly, a package substrate and methods for fabricating the same are disclosed herein. In one example, a chip package assembly includes a package substrate, an IC die and a stiffener. The package substrate includes a first dam projecting from a top surface of the package substrate. The IC die and the stiffener are mounted to the top surface of the package substrate. The stiffener includes a bottom surface that is disposed adjacent to the first dam. At least one surface mounted component is mounted to a region of the package substrate defined between the stiffener and the IC die. An adhesive coupling the stiffener to the package substrate is in contact with the first dam.

公开(公告)号：US09385106B1

公开(公告)日：2016-07-05

申请号：US14444661

申请日：2014-07-28

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Inderjit Singh ,  Glenn O'Rourke ,  Ganesh Hariharan

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/304 ,  H01L23/60

CPC classification number: H01L24/97 ,  H01L21/304 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/60 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected stacked silicon component; encapsulating the unprotected stacked silicon component with a mold compound to cover at least a top surface of the die; grinding the mold compound to reduce a thickness of the mold compound; bonding a carrier wafer to the mold compound; removing the carrier wafer from the mold compound; and removing the mold compound from the top surface of the die after the carrier wafer is removed from the mold compound, to expose the top surface of the die.

Abstract translation: 一种在集成电路形成期间向管芯提供电荷保护的方法，包括将管芯结合到插入件以形成未受保护的堆叠硅部件; 用模具化合物封装未保护的堆叠硅组件以覆盖模具的至少顶表面; 研磨模具化合物以减少模具化合物的厚度; 将载体晶片结合到模具化合物; 从模具化合物中除去载体晶片; 以及在从模具化合物上移除载体晶片之后从模具顶表面去除模具化合物，以露出模具的顶表面。