公开(公告)号：US11323108B1

公开(公告)日：2022-05-03

申请号：US17107572

申请日：2020-11-30

Applicant: XILINX, INC.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Ionut C. Cical

IPC: H04L25/02 ,  H03K5/133 ,  H03K3/037 ,  H05K1/02 ,  G06F13/40

Abstract: A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive− voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

公开(公告)号：US11190178B1

公开(公告)日：2021-11-30

申请号：US17083191

申请日：2020-10-28

Applicant: XILINX, INC.

Inventor： Diarmuid Collins ,  Edward Cullen ,  Ionut C. Cical

IPC: H03K17/16 ,  H03K17/687 ,  H03K17/693 ,  G05F1/10 ,  G05F1/12 ,  H03K17/08 ,  H03K17/06

Abstract: Examples described herein provide an apparatus having a circuit with a grounding circuit and a switch. The apparatus generally includes a gate induced drain leakage (GIDL) protection circuit coupled to the switch and to an output voltage. The GIDL protection circuit may include a switch protection circuit configured to maintain a drain voltage of the switch less than a first supply voltage (Vdd) when the circuit is in an OFF state; and a ground protection circuit configured to maintain a drain voltage of the grounding circuit less than the first supply voltage when the circuit is in an ON state.

公开(公告)号：US10418994B1

公开(公告)日：2019-09-17

申请号：US15647756

申请日：2017-07-12

Applicant: Xilinx, Inc.

Inventor： Edward Cullen ,  Ionut C. Cical

IPC: H03K19/00 ,  H03K19/177

Abstract: A circuit for extending the bandwidth of a termination block is described. The circuit comprises an I/O contact configured to receive an input signal; and a termination circuit coupled to the I/O contact, wherein the termination circuit comprises a plurality of trim legs coupled between a power supply and the I/O contact, each trim leg having a switch to control the impedance in the trim leg.

公开(公告)号：US20160277019A1

公开(公告)日：2016-09-22

申请号：US14659747

申请日：2015-03-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Chandrika Durbha

IPC: H03K17/16 ,  H03K3/012

CPC classification number: H03K17/161 ,  H03K3/012 ,  H03K17/063 ,  H03K17/165 ,  H03K2217/0054

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

Abstract translation: 在一个示例中，一种装置包括具有与开关输入和开关输出之间的p型金属氧化物半导体（PMOS）电路并联的n型金属氧化物半导体（NMOS）电路的模拟开关。 模拟开关响应于确定其开关状态的使能信号。 NMOS电路包括耦合到缓冲器N沟道晶体管的开关N沟道晶体管，耦合到使能信号的开关N沟道晶体管的栅极和耦合到调制N沟道的缓冲器N沟道晶体管的栅极 栅极电压。 PMOS电路包括耦合到缓冲器P沟道晶体管的开关P沟道晶体管，耦合到使能信号的补码的开关P沟道晶体管的栅极和耦合到调制的P沟道晶体管的缓冲器P沟道晶体管的栅极 P沟道栅极电压。 控制电路耦合到模拟开关以提供调制的N沟道和调制的P沟道栅极电压，其中每个沟道栅极电压基于开关状态在相应的电源电压和相应的栅极感应漏极泄漏（GIDL）缓解电压之间交替。

公开(公告)号：US09184623B1

公开(公告)日：2015-11-10

申请号：US14694862

申请日：2015-04-23

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings

IPC: H03L7/06 ,  H02J7/34 ,  H02J7/00 ,  H03K17/56

CPC classification number: H02J7/34 ,  H02J7/0016 ,  H02J7/0072 ,  H02J7/345 ,  H03K4/502 ,  H03K7/08 ,  H03K17/163 ,  H03K17/56 ,  H03L7/0893

Abstract: A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described.

Abstract translation: 描述了用于在集成电路中实现充电/放电开关的电路。 电路包括耦合到第一节点的电源偏置路径，其中电源偏置路径向第一节点提供充电偏置电流; 连接在所述第一节点和电容器的第一端子之间的充电晶体管; 耦合在所述第一节点和地电位之间的充电开关，其中所述充电开关使得能够通过所述第一节点对所述电容器进行充电; 连接在电容器的第一端子和第二节点之间的放电晶体管; 耦合在所述第二节点和参考电压之间的放电开关，其中所述放电开关使得能够通过所述第二节点放电所述电容器; 以及耦合在所述第二节点和地之间的接地偏置路径，其中所述接地偏置路径向所述第二节点提供放电偏置电流。 还描述了在集成电路中实现充电/放电开关的方法。

公开(公告)号：US10608630B1

公开(公告)日：2020-03-31

申请号：US16019150

申请日：2018-06-26

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  Diarmuid Collins ,  John K. Jennings

IPC: H03K17/687 ,  H03K17/16 ,  G05F1/44 ,  H03M1/34

Abstract: A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.

公开(公告)号：US10236873B2

公开(公告)日：2019-03-19

申请号：US14659747

申请日：2015-03-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Chandrika Durbha

IPC: H03K17/16 ,  H03K17/06 ,  H03K3/012

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

公开(公告)号：US20170346455A1

公开(公告)日：2017-11-30

申请号：US15167197

申请日：2016-05-27

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Diarmuid Collins ,  Edward Cullen ,  Ionut C. Cical

IPC: H03F3/45 ,  H03F1/56

CPC classification number: H03F3/45179 ,  H03F1/301 ,  H03F1/56 ,  H03F3/45183 ,  H03F2200/459 ,  H03F2203/45288

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

公开(公告)号：US09245886B2

公开(公告)日：2016-01-26

申请号：US13941419

申请日：2013-07-12

Applicant: Xilinx, Inc.

Inventor： John K. Jennings ,  Ionut C. Cical

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/78 ,  H03K17/06 ,  H03K17/0812 ,  H03K17/693

CPC classification number: H01L27/092 ,  H01L29/78 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/693 ,  H03K2017/066 ,  H03K2217/0054

Abstract: Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit. A source of the first p-type metal oxide semiconductor transistor is connected to an input of the device. The first circuit is for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated.

Abstract translation: 公开了用于将输入与输出隔离的装置。 例如，器件包括第一p型金属氧化物半导体晶体管和第一电路。 第一p型金属氧化物半导体晶体管的源极连接到器件的输入。 第一电路用于当使能信号被去激活并且将接地电压传送到第一p型金属氧化物半导体晶体管的栅极时将器件的输入端上的信号传送到第一p型金属氧化物半导体晶体管的栅极 半导体晶体管当使能信号被激活时。

公开(公告)号：US20150014779A1

公开(公告)日：2015-01-15

申请号：US13941419

申请日：2013-07-12

Applicant: Xilinx, Inc.

Inventor： John K. Jennings ,  Ionut C. Cical

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L29/78 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/693 ,  H03K2017/066 ,  H03K2217/0054

Abstract: Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit. A source of the first p-type metal oxide semiconductor transistor is connected to an input of the device. The first circuit is for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated.

Abstract translation: 公开了用于将输入与输出隔离的装置。 例如，器件包括第一p型金属氧化物半导体晶体管和第一电路。 第一p型金属氧化物半导体晶体管的源极连接到器件的输入。 第一电路用于当使能信号被去激活并且将接地电压传送到第一p型金属氧化物半导体晶体管的栅极时将器件的输入端上的信号传送到第一p型金属氧化物半导体晶体管的栅极 半导体晶体管当使能信号被激活时。