公开(公告)号：US10705144B1

公开(公告)日：2020-07-07

申请号：US16535713

申请日：2019-08-08

Applicant: Xilinx, Inc.

Inventor： John K. Jennings

IPC: H03K19/003 ,  G01R31/3177 ,  H03K19/17724 ,  G01R31/317 ,  H03M1/06 ,  H03M1/10

Abstract: Systems and methods for monitoring operating conditions of a programmable device are disclosed. The system may include a root monitor configured to generate a reference voltage, a plurality of sensors distributed across the device, and a plurality of satellite monitors distributed across the device. Each of the satellite monitors may be coupled to a corresponding sensor via a local interconnect, and may be configured to convert analog signals generated by the sensor into digital data indicative of one or more operating conditions of an associated circuit. In some implementations, each satellite monitor may include a circuit to store a local reference voltage, an analog-to-digital converter (ADC) to convert the analog signals into digital codes, a calibration circuit to generate a correction factor indicative of errors in the digital codes, and a correction circuit to correct the digital codes based on the correction factor.

公开(公告)号：US10598729B1

公开(公告)日：2020-03-24

申请号：US16535726

申请日：2019-08-08

Applicant: Xilinx, Inc.

Inventor： John K. Jennings

IPC: G01R31/3177 ,  H03K19/177 ,  H03K19/17724 ,  G01R31/317 ,  H03M1/06 ,  H03M1/10

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

公开(公告)号：US10054968B2

公开(公告)日：2018-08-21

申请号：US15266947

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  John K. Jennings

IPC: G05F1/10 ,  G05F3/02 ,  G05F1/46

CPC classification number: G05F1/468 ,  G05F3/30

Abstract: An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (BJT) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. The reference voltage circuit includes a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.

公开(公告)号：US09575111B1

公开(公告)日：2017-02-21

申请号：US13942626

申请日：2013-07-15

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Michael J. Hart ,  John K. Jennings

IPC: H02H3/00 ,  G01R31/26 ,  H02H3/20 ,  H03K17/08

CPC classification number: G01R31/26 ,  H02H3/00 ,  H02H3/20 ,  H03K17/08 ,  H03K19/00369

Abstract: A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.

Abstract translation: 配置用于检测集成电路内的过电压事件的系统包括：比较器，被配置为确定所监视的信号的监测电压电平是否超过过应力参考电压电平。 超应力参考电压电平是高于监视信号的额定电压电平的预定量的电压。 该系统还包括耦合到比较器的输出的写入电路。 写电路被配置为响应于比较器确定监视的电压电平超过过应力参考电压电平来指示集成电路内的电应力事件的发生。

公开(公告)号：US20160277019A1

公开(公告)日：2016-09-22

申请号：US14659747

申请日：2015-03-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Chandrika Durbha

IPC: H03K17/16 ,  H03K3/012

CPC classification number: H03K17/161 ,  H03K3/012 ,  H03K17/063 ,  H03K17/165 ,  H03K2217/0054

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

Abstract translation: 在一个示例中，一种装置包括具有与开关输入和开关输出之间的p型金属氧化物半导体（PMOS）电路并联的n型金属氧化物半导体（NMOS）电路的模拟开关。 模拟开关响应于确定其开关状态的使能信号。 NMOS电路包括耦合到缓冲器N沟道晶体管的开关N沟道晶体管，耦合到使能信号的开关N沟道晶体管的栅极和耦合到调制N沟道的缓冲器N沟道晶体管的栅极 栅极电压。 PMOS电路包括耦合到缓冲器P沟道晶体管的开关P沟道晶体管，耦合到使能信号的补码的开关P沟道晶体管的栅极和耦合到调制的P沟道晶体管的缓冲器P沟道晶体管的栅极 P沟道栅极电压。 控制电路耦合到模拟开关以提供调制的N沟道和调制的P沟道栅极电压，其中每个沟道栅极电压基于开关状态在相应的电源电压和相应的栅极感应漏极泄漏（GIDL）缓解电压之间交替。

公开(公告)号：US09184623B1

公开(公告)日：2015-11-10

申请号：US14694862

申请日：2015-04-23

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings

IPC: H03L7/06 ,  H02J7/34 ,  H02J7/00 ,  H03K17/56

CPC classification number: H02J7/34 ,  H02J7/0016 ,  H02J7/0072 ,  H02J7/345 ,  H03K4/502 ,  H03K7/08 ,  H03K17/163 ,  H03K17/56 ,  H03L7/0893

Abstract: A circuit for implementing a charge/discharge switch in an integrated circuit is described. The circuit comprises a supply bias path coupled to a first node, wherein the supply bias path provides a charging bias current to the first node; a charge transistor connected between the first node and a first terminal of a capacitor; a charge switch coupled between the first node and a ground potential, wherein the charge switch enables charging of the capacitor by way of the first node; a discharge transistor connected between the first terminal of the capacitor and a second node; a discharge switch coupled between the second node and a reference voltage, wherein the discharge switch enables discharging of the capacitor by way of the second node; and a ground bias path coupled between the second node and ground, wherein the ground bias path provides a discharging bias current to the second node. A method of implementing a charge/discharge switch in an integrated circuit is also described.

Abstract translation: 描述了用于在集成电路中实现充电/放电开关的电路。 电路包括耦合到第一节点的电源偏置路径，其中电源偏置路径向第一节点提供充电偏置电流; 连接在所述第一节点和电容器的第一端子之间的充电晶体管; 耦合在所述第一节点和地电位之间的充电开关，其中所述充电开关使得能够通过所述第一节点对所述电容器进行充电; 连接在电容器的第一端子和第二节点之间的放电晶体管; 耦合在所述第二节点和参考电压之间的放电开关，其中所述放电开关使得能够通过所述第二节点放电所述电容器; 以及耦合在所述第二节点和地之间的接地偏置路径，其中所述接地偏置路径向所述第二节点提供放电偏置电流。 还描述了在集成电路中实现充电/放电开关的方法。

公开(公告)号：US08922412B1

公开(公告)日：2014-12-30

申请号：US13874040

申请日：2013-04-30

Applicant: Xilinx, Inc.

Inventor： Christopher M. Gorman ,  April M. Graham ,  John K. Jennings

IPC: H03M1/66

CPC classification number: H03M1/0604 ,  H03M1/662 ,  H03M1/742

Abstract: An apparatus relating generally to digital-to-analog conversion is disclosed. In such an apparatus, a digital-to-analog converter (“DAC”) device includes a source DAC and a sink DAC selectively coupled to one another. The source DAC provides a first bias to the sink DAC in a sink mode, and the sink DAC provides a second bias to the source DAC in a source mode.

Abstract translation: 公开了一般涉及数模转换的装置。 在这种装置中，数模转换器（“DAC”）装置包括一个选择性地耦合到彼此的源DAC和信宿DAC。 源DAC在宿模式中向宿DAC提供第一偏置，并且宿DAC在源模式中向源DAC提供第二偏置。

公开(公告)号：US11199581B1

公开(公告)日：2021-12-14

申请号：US16809399

申请日：2020-03-04

Applicant: Xilinx, Inc.

Inventor： John K. Jennings

IPC: G01R31/3177 ,  H03M1/06 ,  H03K19/17724 ,  G01R31/317 ,  H03M1/10

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

公开(公告)号：US10545053B2

公开(公告)日：2020-01-28

申请号：US15616765

申请日：2017-06-07

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Padraig Kelly ,  John K. Jennings

IPC: G01K7/00 ,  G01K7/01 ,  H03K19/003 ,  H03K19/0175 ,  G01K1/02

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

公开(公告)号：US20190172504A1

公开(公告)日：2019-06-06

申请号：US15832515

申请日：2017-12-05

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  John K. Jennings ,  Edward Cullen ,  Ionut C. Cical ,  Darragh Walsh

IPC: G11C5/14 ,  G01K7/01 ,  G05F3/24

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the complementary-to-temperature current.