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    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES
    12.
    发明申请
    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES 审中-公开

    公开(公告)号：US20200066713A1

    公开(公告)日：2020-02-27

    申请号：US16110894

    申请日：2018-08-23

    Applicant: Xilinx, Inc.

    Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

    IPC: H01L27/06 ,  H01L27/02 ,  H01L29/73 ,  H01L29/78 ,  H01L49/02

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

    Circuit for and method of storing data in an integrated circuit device
    14.
    发明授权
    Circuit for and method of storing data in an integrated circuit device 有权

    公开(公告)号：US10263623B1

    公开(公告)日：2019-04-16

    申请号：US16107751

    申请日：2018-08-21

    Applicant: Xilinx, Inc.

    Inventor： Yanran Chen ,  Pierre Maillard ,  Michael J. Hart

    IPC: G11C17/18 ,  H03K19/173 ,  H03K17/00 ,  G11C11/412 ,  H03K19/003

    Abstract: A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described.

    Circuit for and method of preventing multi-bit upsets induced by single event transients
    15.
    发明授权
    Circuit for and method of preventing multi-bit upsets induced by single event transients 有权

    公开(公告)号：US09825632B1

    公开(公告)日：2017-11-21

    申请号：US15228981

    申请日：2016-08-04

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Michael J. Hart ,  Praful Jain ,  Robert I. Fu

    IPC: H03K19/003 ,  H03K19/177

    CPC classification number: H03K19/00315 ,  H03K19/17728 ,  H03K19/1776

    Abstract: A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

    Mitigation of single event latchup
    16.
    发明授权
    Mitigation of single event latchup 有权

    公开(公告)号：US09793899B1

    公开(公告)日：2017-10-17

    申请号：US15382385

    申请日：2016-12-16

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Jue Arver ,  Michael J. Hart ,  John K. Jennings

    IPC: H03K19/003 ,  H03K19/177

    CPC classification number: H03K19/17764 ,  H03K19/0033

    Abstract: The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

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