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    Circuits for and methods of controlling power within an integrated circuit
    11.
    发明授权
    Circuits for and methods of controlling power within an integrated circuit 有权
    用于控制集成电路内电源的电路和方法

    公开(公告)号：US09438244B2

    公开(公告)日：2016-09-06

    申请号：US14526192

    申请日：2014-10-28

    Applicant: Xilinx, Inc.

    Inventor： Santosh Kumar Sood ,  Brian C. Gaide ,  Steven P. Young

    IPC: G05F1/10 ,  H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/17784 ,  H03K19/0008 ,  H03K19/0016

    Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

    Abstract translation: 用于控制集成电路内的电力的电路包括多个电路块; 在集成电路内布线的全局控制信号; 和多个功率控制块。 每个功率控制块耦合到多个电路块的相应电路块，并且具有耦合以接收参考电压的第一输入和耦合以接收全局控制信号的第二输入。 对于每个电路块，全局控制信号使得参考电压与对应的电路块的耦合。 还公开了一种控制集成电路内的功率的方法。

    CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED CIRCUIT
    13.
    发明申请
    CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED CIRCUIT 有权
    在集成电路中控制电源的电路和方法

    公开(公告)号：US20160118988A1

    公开(公告)日：2016-04-28

    申请号：US14526192

    申请日：2014-10-28

    Applicant: Xilinx, Inc.

    Inventor： Santosh Kumar Sood ,  Brian C. Gaide ,  Steven P. Young

    IPC: H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/17784 ,  H03K19/0008 ,  H03K19/0016

    Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

    Abstract translation: 用于控制集成电路内的电力的电路包括多个电路块; 在集成电路内布线的全局控制信号; 和多个功率控制块。 每个功率控制块耦合到多个电路块的相应电路块，并且具有耦合以接收参考电压的第一输入和耦合以接收全局控制信号的第二输入。 对于每个电路块，全局控制信号使得参考电压与对应的电路块的耦合。 还公开了一种控制集成电路内的功率的方法。

    Two gate pitch FPGA memory cell
    14.
    发明授权
    Two gate pitch FPGA memory cell 有权
    两个门间距FPGA存储单元

    公开(公告)号：US09177634B1

    公开(公告)日：2015-11-03

    申请号：US14172835

    申请日：2014-02-04

    Applicant: Xilinx, Inc.

    Inventor： Steven P. Young ,  Yang Song ,  Nui Chong

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/41 ,  H03K19/177

    CPC classification number: H01L27/0207 ,  G11C11/41 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/177 ,  H03K19/1776

    Abstract: A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.

    Abstract translation: 存储单元包括第一反相器和第二反相器，其中第一反相器和第二反相器使用存储节点和反向存储节点进行交叉耦合; 数据节点和逆数据节点，其中所述数据节点和逆数据节点在所述存储器单元的第一侧旁边; 以及地址线，其通过数据和逆数据节点控制对存储节点和逆存储节点的访问; 其中所述存储单元包括两个门间距存储单元。

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