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113 条记录 (耗时 0.044 秒)

    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07430149B2

    公开(公告)日：2008-09-30

    申请号：US11503941

    申请日：2006-08-15

    申请人： Kenji Yoshinaga ,  Fukashi Morishita

    发明人： Kenji Yoshinaga ,  Fukashi Morishita

    IPC分类号： G11C5/01

    CPC分类号： G11C5/147

    摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

    摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据通路。

    Semiconductor device
    12.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20070047365A1

    公开(公告)日：2007-03-01

    申请号：US11503941

    申请日：2006-08-15

    申请人： Kenji Yoshinaga ,  Fukashi Morishita

    发明人： Kenji Yoshinaga ,  Fukashi Morishita

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

    摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据通路。

    Semiconductor device
    15.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06914300B2

    公开(公告)日：2005-07-05

    申请号：US10653198

    申请日：2003-09-03

    申请人： Masakazu Hirose ,  Fukashi Morishita

    发明人： Masakazu Hirose ,  Fukashi Morishita

    IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L27/01 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L31/0392

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.

    摘要翻译： 在潜在的互连层中，当从平面观察时，交替地设置多个电源电位区域和接地电位区域，层间绝缘层位于其间。 提供穿透第二绝缘层的接触插塞以将选定的场效应晶体管的一侧上的源极/漏极（S / D）区域与选定的电源电位区域电连接。 类似地，穿过第二绝缘层的接触插塞被提供以将另一个选择的场效应晶体管的另一侧上的源极/漏极（S / D）区域与选择的接地电位区域电连接。 通过采用这种结构，提供了具有能够稳定电源电位和接地电位的多个半导体电路的半导体器件，而与半导体器件的横截面结构无关。

    Clock generating circuit
    16.
    发明授权
    Clock generating circuit 失效
    时钟发生电路

    公开(公告)号：US06781431B2

    公开(公告)日：2004-08-24

    申请号：US10349033

    申请日：2003-01-23

    申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mihoko Akiyama ,  Mako Okamoto

    IPC分类号： G06F104

    CPC分类号： H03K3/0315 ,  H02M3/07 ,  H03K3/013 ,  H03K3/70

    摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.

    摘要翻译： 用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。 当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。 锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。 当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

    Semiconductor device reduced in through current
    18.
    发明授权
    Semiconductor device reduced in through current 失效
    半导体器件通过电流减小

    公开(公告)号：US06483357B2

    公开(公告)日：2002-11-19

    申请号：US09811578

    申请日：2001-03-20

    申请人： Hiroshi Kato ,  Fukashi Morishita

    发明人： Hiroshi Kato ,  Fukashi Morishita

    IPC分类号： H03L700

    CPC分类号： G05F1/465

    摘要： A sense signal IVOFF is generated by a power supply level sense circuit with an external power supply potential Ext.Vcc1 as the operating power supply potential to sense the level of an external power supply potential Ext.Vcc2. By suppressing generation of an internal power supply potential or fixing the internal node by the sense signal IVOFF, the through current at the time of power on can be reduced.

    摘要翻译： 感测信号IVOFF由电源电平检测电路产生，外部电源电位Ext.Vcc1作为工作电源电位，用于感测外部电源电位Ext.Vcc2的电平。 通过抑制内部电源电位的产生或通过感测信号IVOFF固定内部节点，可以减少上电时的通过电流。