公开(公告)号：US06468865B1

公开(公告)日：2002-10-22

申请号：US09723653

申请日：2000-11-28

Applicant: Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

Inventor： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

Abstract translation: 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

公开(公告)号：US06445030B1

公开(公告)日：2002-09-03

申请号：US09772600

申请日：2001-01-30

Applicant: Yider Wu ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Che-Hoo Ng

Inventor： Yider Wu ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Che-Hoo Ng

IPC: H01L2972

CPC classification number: H01L21/28211 ,  H01L21/28282 ,  H01L29/511 ,  H01L29/792

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a silicon substrate; a tunnel oxide layer over the silicon substrate, the tunnel oxide layer comprising fluorine atoms; a charge trapping layer over the tunnel oxide layer; an electrode or poly layer over the charge trapping layer; and source and drain regions within the silicon substrate. Another aspect of the present invention relates to a method of making a non-volatile semiconductor memory cell having improved erase speed, involving the steps of providing a silicon substrate; forming a tunnel oxide layer comprising fluorine atoms over the silicon substrate; and forming non-volatile memory cells over the tunnel oxide layer.

Abstract translation: 本发明的一个方面涉及一种包含硅衬底的非易失性半导体存储器件; 硅衬底上的隧道氧化物层，所述隧道氧化物层包含氟原子; 在隧道氧化物层上方的电荷捕获层; 在电荷捕获层上方的电极或多晶硅层; 以及硅衬底内的源区和漏区。 本发明的另一方面涉及一种制造具有改善的擦除速度的非易失性半导体存储单元的方法，包括提供硅衬底的步骤; 在所述硅衬底上形成包含氟原子的隧道氧化物层; 以及在所述隧道氧化物层上形成非易失性存储单元。

公开(公告)号：US06417082B1

公开(公告)日：2002-07-09

申请号：US09651684

申请日：2000-08-30

Applicant: Yider Wu ,  Jean Yang ,  Hidehiko Shiraiwa ,  Mark E. Ramsbey

Inventor： Yider Wu ,  Jean Yang ,  Hidehiko Shiraiwa ,  Mark E. Ramsbey

IPC: H01L21425

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/26586

Abstract: A process for making a semiconductor structure comprises implanting nitrogen through a layer comprising SiO2 into a substrate comprising Si, wherein the layer is on the substrate, and wherein the layer is from about 30 Å to about 300 Å thick.

Abstract translation: 制造半导体结构的方法包括将氮通过包含SiO 2的层注入到包含Si的衬底中，其中该层在衬底上，并且其中该层为约30埃至约300埃。

公开(公告)号：US06403420B1

公开(公告)日：2002-06-11

申请号：US09627664

申请日：2000-07-28

Applicant: Jean Yang ,  Yider Wu ,  Mark Ramsbey ,  Yu Sun

Inventor： Jean Yang ,  Yider Wu ,  Mark Ramsbey ,  Yu Sun

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76202 ,  H01L27/115 ,  H01L29/66833

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.

Abstract translation: 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 在ONO层和接合区域已经形成之后注入氮。 整个半导体结构被加热以退出氮注入损伤，并将注入的氮扩散或驱动到衬底和氧化硅界面中，以在该界面处形成强的SiN键。 通过将氮气注入到ONO堆叠中，代替如常规制造的单个氧化硅层，降低了底层硅衬底的损坏。 这导致相邻位线之间更好的隔离并且抑制相邻位线之间的泄漏。

公开(公告)号：US06362051B1

公开(公告)日：2002-03-26

申请号：US09648361

申请日：2000-08-25

Applicant: Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

Inventor： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

IPC: H01L21336

CPC classification number: H01L21/28202 ,  H01L21/26533 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract translation: 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。 在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

公开(公告)号：US06284600B1

公开(公告)日：2001-09-04

申请号：US09609468

申请日：2000-07-03

Applicant: Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

Inventor： Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

Abstract translation: 将诸如氮的预定物质放置在闪存存储器件的控制电介质结构的位线结和电介质层之间的界面处，以通过在编程或擦除操作期间最小化界面缺陷的形成来最小化这种界面的劣化 闪存设备。 将诸如氮的预定物质注入到闪速存储器件的位线结中。 执行加热半导体晶片的热处理，使得在热处理期间注入到半导体晶片内的预定物质例如氮漂移到位线结与控制电介质结构之间的界面。 在闪存器件的编程或擦除操作期间，预定种类例如接口处的氮使界面缺陷的形成最小化，从而使界面的时效性降低。

公开(公告)号：US20100227460A1

公开(公告)日：2010-09-09

申请号：US12399377

申请日：2009-03-06

Applicant: Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

Inventor： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC: H01L21/4763

CPC classification number: H01L27/11521 ,  H01L21/76224

Abstract: In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

Abstract translation: 在制造NOR闪速存储器的方法中，当存储器件尺寸进一步减小时，省略在栅极结构的两个侧面处形成间隔物，并且两个栅极结构之间的间隔可以直接用介电间隔件 或浅沟槽隔离（STI）层。 因此，可以避免在栅极结构之间的极小空间中形成间隔物而造成存储器件制造难度增大的问题。 该方法还能够省略形成硅化物层所需的自对准步骤。 因此，也可以避免由于栅极结构之间的极小空间而导致的自对准难度。

公开(公告)号：US20100099262A1

公开(公告)日：2010-04-22

申请号：US12254022

申请日：2008-10-20

Applicant: Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

Inventor： Yi-Hsiu Chen ,  Yung-Chung Lee ,  Yider Wu

IPC: H01L21/3105

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  Y10S438/976

Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract translation: 在制造非易失性存储单元的方法中，使用自对准金属硅化物代替常规钨金属层以形成多晶硅栅极，并且自对准金属硅化物用作多晶硅上的连接层 门。 通过使用自对准的金属硅化物来形成多晶硅栅极，可以节省在蚀刻工艺中使用掩模，从而能够简化制造工艺，从而降低制造成本。 同时，可以避免由氧化的钨金属层引起的电阻偏移的问题。

公开(公告)号：US07529132B2

公开(公告)日：2009-05-05

申请号：US11762369

申请日：2007-06-13

Applicant: Chao Yang Chen ,  Yider Wu ,  Hsiao Hua Lu

Inventor： Chao Yang Chen ,  Yider Wu ,  Hsiao Hua Lu

IPC: G11C11/34

CPC classification number: G11C16/0433

Abstract: A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.

Abstract translation: 单聚多边形非易失性存储器包括存储节点，控制节点和浮动门。 当执行编程操作时，位线被提供有低电压，并且控制线被提供有高电压，使得在浮动栅极中发生耦合电压。 浮动栅极和存储节点之间的电压差能够将电子发送到浮动栅极，但是浮动栅极和控制节点之间的电压差不足以从浮动栅极排出电子。 当执行擦除操作时，位线被提供有高电压，并且控制线设置有低电压，使得在浮动栅极上发生耦合电压。 浮栅和存储节点之间的电压差能够从浮置栅极排出电子，但是浮栅和控制节点之间的电压差不足以将电子发送到浮置栅极。

公开(公告)号：US20090086548A1

公开(公告)日：2009-04-02

申请号：US11866018

申请日：2007-10-02

Applicant: Yider Wu ,  Yung-Chung Lee

Inventor： Yider Wu ,  Yung-Chung Lee

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time.

Abstract translation: 应用于NAND和/或NOR闪速存储器的闪速存储器具有氧化硅 - 氮化物 - 氧化物 - 硅电池结构，其通道 - 热电子注入作为其写入机制具有局部捕获特性，并且使用热孔 注射作为其擦除机制。 闪速存储器使用氧化物 - 氮化物 - 氧化物结构来代替浮动栅极，从而解决了浮栅的局部泄漏引起的整个泄漏的问题。 闪存可以小型化而没有数据相互干扰的问题，并且可以容易地集成到CMOS工艺中以大大降低其制造成本。 同时，闪存还可以实现更快的编程时间和擦除时间。