公开(公告)号：US06445030B1

公开(公告)日：2002-09-03

申请号：US09772600

申请日：2001-01-30

申请人： Yider Wu ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Che-Hoo Ng

发明人： Yider Wu ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Che-Hoo Ng

IPC分类号： H01L2972

CPC分类号： H01L21/28211 ,  H01L21/28282 ,  H01L29/511 ,  H01L29/792

摘要： One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a silicon substrate; a tunnel oxide layer over the silicon substrate, the tunnel oxide layer comprising fluorine atoms; a charge trapping layer over the tunnel oxide layer; an electrode or poly layer over the charge trapping layer; and source and drain regions within the silicon substrate. Another aspect of the present invention relates to a method of making a non-volatile semiconductor memory cell having improved erase speed, involving the steps of providing a silicon substrate; forming a tunnel oxide layer comprising fluorine atoms over the silicon substrate; and forming non-volatile memory cells over the tunnel oxide layer.

摘要翻译： 本发明的一个方面涉及一种包含硅衬底的非易失性半导体存储器件; 硅衬底上的隧道氧化物层，所述隧道氧化物层包含氟原子; 在隧道氧化物层上方的电荷捕获层; 在电荷捕获层上方的电极或多晶硅层; 以及硅衬底内的源区和漏区。 本发明的另一方面涉及一种制造具有改善的擦除速度的非易失性半导体存储单元的方法，包括提供硅衬底的步骤; 在所述硅衬底上形成包含氟原子的隧道氧化物层; 以及在所述隧道氧化物层上形成非易失性存储单元。

公开(公告)号：US06642152B1

公开(公告)日：2003-11-04

申请号：US09812206

申请日：2001-03-19

申请人： Che-Hoo Ng ,  Scott Bell ,  Anne Sanderfer ,  Christopher Lee Pike

发明人： Che-Hoo Ng ,  Scott Bell ,  Anne Sanderfer ,  Christopher Lee Pike

IPC分类号： H01L21302

CPC分类号： H01L21/0338 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144

摘要： The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about 2500 Å formed over a semiconductor structure. In one aspect of the present invention, the method includes providing a semiconductor substrate having a device film layer formed thereon. An ultra thin resist is then deposited over the device film layer. The ultra thin resist is patterned according to a desired structure or feature using conventional photolithography techniques. Following development, the ultra thin resist is implanted with a dopant. After the implantation is substantially completed, the device film layer is anisotropically etched.

摘要翻译： 本发明涉及一种降低超薄抗蚀剂特征的线宽的系统和方法。 本发明通过对在半导体结构上形成的厚度小于约2500埃的超薄抗蚀剂施加致密化工艺来实现这一目的。 在本发明的一个方面，该方法包括提供其上形成有器件膜层的半导体衬底。 然后将超薄抗蚀剂沉积在器件膜层上。 根据期望的结构或特征，使用常规光刻技术将超薄抗蚀剂图案化。 在显影之后，用超声波光刻胶注入掺杂剂。 在基本完成注入之后，将各向异性蚀刻器件膜层。

公开(公告)号：US06380041B1

公开(公告)日：2002-04-30

申请号：US09686476

申请日：2000-10-10

申请人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

发明人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

IPC分类号： H01L21336

CPC分类号： H01L29/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045

摘要： An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

摘要翻译： 具有横向不均匀沟道掺杂分布的超大规模集成电路半导体器件通过以垂直于0°至60°的注入角度使用IV族元件注入来制造，以在掺杂硅衬底中产生间隙 半导体器件的栅极。 在创建间隙之后，使用也与从垂直方向成0°至60°的植入角度植入的III族或V族元件进行沟道掺杂注入。 然后使用快速热退火来通过瞬时增强的扩散将掺杂剂横向驱动到半导体器件的沟道中。

公开(公告)号：US6008098A

公开(公告)日：1999-12-28

申请号：US726113

申请日：1996-10-04

申请人： Shekhar Pramanick ,  Che-Hoo Ng

发明人： Shekhar Pramanick ,  Che-Hoo Ng

IPC分类号： H01L21/265 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513

摘要： A method of achieving shallow junctions in a semiconductor device is achieved by providing an amorphous silicon layer over an epitaxial layer, implanting ions into the amorphous silicon layer, and annealing the resulting device to recrystallize the amorphous silicon layer and drive in the implanted ions to a shallow depth less than the depth of the amorphous silicon layer.

摘要翻译： 在半导体器件中实现浅结的方法是通过在外延层上提供非晶硅层，将离子注入到非晶硅层中，并对所得器件进行退火以使非晶硅层再结晶并将注入的离子驱动到 浅深度小于非晶硅层的深度。

公开(公告)号：US06756600B2

公开(公告)日：2004-06-29

申请号：US09252845

申请日：1999-02-19

申请人： Che-Hoo Ng ,  Emi Ishida ,  Jaime M. Reyes ,  Jinning Liu ,  Sandeep Mehta

发明人： Che-Hoo Ng ,  Emi Ishida ,  Jaime M. Reyes ,  Jinning Liu ,  Sandeep Mehta

IPC分类号： H01J3708

CPC分类号： H01J27/08 ,  H01J37/08 ,  H01J2237/31701

摘要： A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.

摘要翻译： 在离子注入系统中增加离子源寿命的方法使用惰性气体（例如氩或氙）引入含卤素源气体中。 惰性气体组分通过增强溅射在等离子体环境中具有清洁效果。

公开(公告)号：US06514833B1

公开(公告)日：2003-02-04

申请号：US09667600

申请日：2000-09-22

申请人： Emi Ishida ,  Che-Hoo Ng

发明人： Emi Ishida ,  Che-Hoo Ng

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/823878

摘要： Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI) technology enhanced by selectively implanting the bottom surface of the trench with dopant diffusion inhibiting ions prior to filling the trench with a dielectric material and formation of opposite conductivity type well regions on either side of the trench. The inventive methodology effectively reduces or substantially eliminates deleterious counterdoping of the subsequently formed well regions resulting from thermally-induced lateral inter-diffusion of p-type and/or n-type dopant impurities used for forming the well regions.

摘要翻译： 通过利用浅沟槽隔离（STI）技术形成包括形成在公共半导体衬底（例如CMOS器件）中的多个有源器件区域的半导体器件，所述浅沟槽隔离（STI）技术通过在填充之前通过选择性地注入掺杂剂扩散抑制离子的沟槽的底表面来增强 所述沟槽具有电介质材料，并且在沟槽的任一侧上形成相反导电类型的阱区。 本发明的方法有效地减少或基本上消除了由用于形成阱区的p型和/或n型掺杂剂杂质的热诱导的横向相互扩散而导致的随后形成的阱区的有害的反掺杂。

公开(公告)号：US06503801B1

公开(公告)日：2003-01-07

申请号：US09640186

申请日：2000-08-17

申请人： Richard P. Rouse ,  Che-Hoo Ng ,  Judy X. An

发明人： Richard P. Rouse ,  Che-Hoo Ng ,  Judy X. An

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/66659

摘要： A semiconductor device with reduced leakage current is obtained by forming a non-uniform channel doping profile. A high impurity region of the opposite conductive type of a source region is formed between the channel region and source region by transient enhanced diffusion (TED). The high impurity region substantially reduces the threshold voltage rolling off problem.

摘要翻译： 通过形成不均匀的沟道掺杂分布来获得具有减小的漏电流的半导体器件。 通过瞬时增强扩散（TED）在沟道区域和源极区域之间形成相反导电类型的源极区域的高杂质区域。 高杂质区域大大降低了阈值电压下降的问题。

公开(公告)号：US06459141B2

公开(公告)日：2002-10-01

申请号：US09495075

申请日：2000-01-31

申请人： Bin Yu ,  Che-Hoo Ng

发明人： Bin Yu ,  Che-Hoo Ng

IPC分类号： H01L2904

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1079

摘要： The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

摘要翻译： 本发明提供了用于电分离n沟道和p沟道MOSFET的改进的阱结构。 本发明首先在基底中形成浅井。 然后在浅井下面形成掩埋非晶层。 然后在埋入的非晶层下方形成深井。 然后对衬底进行快速热退火以使埋入的非晶层重结晶。 井结构由浅井和深井组成。 然后可以在阱结构之上形成常规的半导体器件。 掩埋非晶层在形成深井期间抑制沟道效应，而不需要倾斜角。

公开(公告)号：US06232048B1

公开(公告)日：2001-05-15

申请号：US09260790

申请日：1999-03-01

申请人： Matthew S. Buynoski ,  Che-Hoo Ng ,  Bhanwar Singh ,  Shekhan Pramanick ,  Subhash Gupta

发明人： Matthew S. Buynoski ,  Che-Hoo Ng ,  Bhanwar Singh ,  Shekhan Pramanick ,  Subhash Gupta

IPC分类号： G03C500

CPC分类号： G03F7/40 ,  G03F7/2024 ,  G03F7/203 ,  H01L21/0274

摘要： A method of preparing a narrow photoresist line by first forming a resist pattern on a substrate, wherein a resist line is designed to have a width “w” in excess of a desired width “w1” The resist is then subjected to ionic bombardment with ionized particles in a direction normal to the planar surface of a resistant substrate. The ionic bombardment causes formation of a hardened “chemically less reactive” skin on the exposed top surface of the photoresist. The resist is then subjected to an isotropic etch procedure. Due to the hardened top surface of the narrow pattern, the side wall erode at a faster rate than the top, causing a narrowing of the line width, while retaining a more substantial photoresist thickness than would occur if the top surface would not be hardened in advance of the etch procedure.

摘要翻译： 一种通过在衬底上首先形成抗蚀剂图案来制备窄光致抗蚀剂线的方法，其中抗蚀剂线被设计成具有超过所需宽度“w1”的宽度“w”。然后将抗蚀剂用离子轰击 颗粒在垂直于耐磨基材的平坦表面的方向上。 离子轰击导致在光致抗蚀剂的暴露的顶表面上形成硬化的“化学反应性较差”的皮肤。 然后对抗蚀剂进行各向同性蚀刻程序。 由于狭窄图案的硬化顶表面，侧壁以比顶部更快的速度侵蚀，导致线宽度变窄，同时保留比如果顶表面不会硬化时更可观察到的光致抗蚀剂厚度 蚀刻过程的进步。

公开(公告)号：US06229177B1

公开(公告)日：2001-05-08

申请号：US09050747

申请日：1998-03-30

申请人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

发明人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

IPC分类号： H01L2976

CPC分类号： H01L29/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045

摘要： An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

摘要翻译： 具有横向不均匀沟道掺杂分布的超大规模集成电路半导体器件通过以垂直于0°至60°的注入角度使用IV族元件注入来制造，以在掺杂硅衬底中产生间隙 半导体器件的栅极。 在创建间隙之后，使用也与从垂直方向成0°至60°的植入角度植入的III族或V族元件进行沟道掺杂注入。 然后使用快速热退火来通过瞬时增强的扩散将掺杂剂横向驱动到半导体器件的沟道中。