公开(公告)号：US06847068B2

公开(公告)日：2005-01-25

申请号：US10441801

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/8242

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

公开(公告)号：US07714445B2

公开(公告)日：2010-05-11

申请号：US11951274

申请日：2007-12-05

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L23/552 ,  H01L21/768

CPC classification number: H01L27/0251 ,  H01L27/10894

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract translation: 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

公开(公告)号：US06855966B2

公开(公告)日：2005-02-15

申请号：US10435416

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L31/072 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底。 在半导体衬底上依次形成栅介电层和导电层。 在导电层上形成具有开口的图案化的硬掩模层，其中导电层的一部分通过开口露出。 间隔件形成在开口的侧壁上。 图案化的硬掩模层被去除。 导电间隔件形成在间隔件的侧壁上。 依次去除暴露的导电层和暴露的栅介质层。

公开(公告)号：US07700991B2

公开(公告)日：2010-04-20

申请号：US11946868

申请日：2007-11-29

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

Abstract translation: 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20090014886A1

公开(公告)日：2009-01-15

申请号：US11951274

申请日：2007-12-05

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L23/522 ,  H01L21/768 ,  H02H9/00

CPC classification number: H01L27/0251 ,  H01L27/10894

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract translation: 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

公开(公告)号：US07576381B2

公开(公告)日：2009-08-18

申请号：US11955397

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L27/108

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract translation: 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US20090014773A1

公开(公告)日：2009-01-15

申请号：US11946868

申请日：2007-11-29

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

Abstract translation: 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20080265302A1

公开(公告)日：2008-10-30

申请号：US11955397

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract translation: 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US07115477B2

公开(公告)日：2006-10-03

申请号：US10884769

申请日：2004-07-02

Applicant: Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L29/512 ,  H01L21/26506 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583

Abstract: A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.

Abstract translation: 具有双栅介质层的栅极及其制造方法。 提供半导体衬底，其上依次形成介电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 离子注入半导体衬底，去除间隔物和暴露的电介质层，并且在开口的底部形成栅极氧化物层。

公开(公告)号：US06893919B2

公开(公告)日：2005-05-17

申请号：US10810740

申请日：2004-03-26

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.