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    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
    12.
    发明申请
    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage 失效
    使用保护层制造鳍状场效应晶体管以减少蚀刻损伤的方法

    公开(公告)号：US20050019993A1

    公开(公告)日：2005-01-27

    申请号：US10869764

    申请日：2004-06-16

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8242

    CPC分类号： H01L29/7851 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底突出的垂直翅片。 缓冲氧化物衬垫形成在翅片的顶表面和侧壁上。 然后在衬底上形成沟槽，其中鳍的至少一部分从沟槽的底表面突出。 可以通过在鳍片的至少一部分上形成伪栅极来形成沟槽，在围绕虚拟栅极的鳍片上形成绝缘层，然后去除伪栅极以暴露鳍片的至少一部分，使得 沟槽被绝缘层包围。 然后从鳍片的突出部分去除缓冲氧化物衬垫，并且在鳍片的突出部分上的沟槽中形成栅极。

    Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions
    13.
    发明申请
    Methods of Fabricating MOS Transistors Having Recesses With Elevated Source/Drain Regions 有权
    制造具有高的源极/漏极区域的凹槽的MOS晶体管的方法

    公开(公告)号：US20120034746A1

    公开(公告)日：2012-02-09

    申请号：US13241311

    申请日：2011-09-23

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions
    14.
    发明申请
    Methods of Fabricating MOS Transistors Having Recesses with Elevated Source/Drain Regions 有权
    制造具有高的源极/漏极区域的凹陷的MOS晶体管的方法

    公开(公告)号：US20100041201A1

    公开(公告)日：2010-02-18

    申请号：US12582073

    申请日：2009-10-20

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Fin field effect transistors having capping insulation layers
    15.
    发明授权
    Fin field effect transistors having capping insulation layers 有权
    Fin场效应晶体管具有封盖绝缘层

    公开(公告)号：US07642589B2

    公开(公告)日：2010-01-05

    申请号：US11433942

    申请日：2006-05-15

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

    摘要： A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

    摘要翻译： 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。

    Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations
    17.
    发明授权
    Integrated circuit field effect transistors including channel-containing fin having regions of high and low doping concentrations 有权
    集成电路场效应晶体管，其包括具有高掺杂浓度和低掺杂浓度区域的含通道翅片

    公开(公告)号：US07122871B2

    公开(公告)日：2006-10-17

    申请号：US10801614

    申请日：2004-03-16

    申请人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66803

    摘要： Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described.

    摘要翻译： 集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。 沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。 源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。 还描述了相关的制造方法。

    Fin field effect transistors including epitaxial fins
    19.
    发明授权
    Fin field effect transistors including epitaxial fins 有权
    Fin场效应晶体管包括外延鳍片

    公开(公告)号：US07394117B2

    公开(公告)日：2008-07-01

    申请号：US11622103

    申请日：2007-01-11

    申请人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    发明人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC分类号： H01L29/34

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Methods of fabricating fin field effect transistors
    20.
    发明授权
    Methods of fabricating fin field effect transistors 有权
    散射场效应晶体管的制造方法

    公开(公告)号：US07176067B2

    公开(公告)日：2007-02-13

    申请号：US10869763

    申请日：2004-06-16

    申请人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    发明人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC分类号： H01L21/339

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。