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公开(公告)号:US07996735B2
公开(公告)日:2011-08-09
申请号:US12469778
申请日:2009-05-21
申请人: Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人: Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号: G11C29/00
CPC分类号: G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译: 为了实现低功耗的快速且高度可靠的相变存储器系统,半导体器件包括:存储器件,其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器,其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件,在多个第二存储单元中执行多次尝试写入,并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。
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公开(公告)号:US20120211718A1
公开(公告)日:2012-08-23
申请号:US13440225
申请日:2012-04-05
申请人: AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人: AKIO SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号: H01L45/00
CPC分类号: H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译: 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构,其中开关晶体管的内部填充有可变电阻元件,特别是相变材料。 通过施加电压来切换开关晶体管,以增加沟道电阻,使得电流在内部相变材料中流动以操作存储器。
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公开(公告)号:US08169819B2
公开(公告)日:2012-05-01
申请号:US12688886
申请日:2010-01-17
申请人: Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人: Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
CPC分类号: H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译: 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构,其中开关晶体管的内部填充有可变电阻元件,特别是相变材料。 通过施加电压来切换开关晶体管,以增加沟道电阻,使得电流在内部相变材料中流动以操作存储器。
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公开(公告)号:US20110283039A1
公开(公告)日:2011-11-17
申请号:US13191442
申请日:2011-07-26
申请人: MOTOYASU TERAO , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人: MOTOYASU TERAO , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号: G06F12/06
CPC分类号: G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译: 为了实现低功耗的快速且高度可靠的相变存储器系统,半导体器件包括:存储器件,其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器,其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件,在多个第二存储单元中执行多次尝试写入,并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。
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公开(公告)号:US20100182828A1
公开(公告)日:2010-07-22
申请号:US12688886
申请日:2010-01-17
申请人: Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人: Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
CPC分类号: H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译: 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构,其中开关晶体管的内部填充有可变电阻元件,特别是相变材料。 通过施加电压来切换开关晶体管,以增加沟道电阻,使得电流在内部相变材料中流动以操作存储器。
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公开(公告)号:US20130228739A1
公开(公告)日:2013-09-05
申请号:US13884263
申请日:2010-12-06
申请人: Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
发明人: Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC分类号: H01L45/00
CPC分类号: H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
摘要: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.
摘要翻译: 当在叠层薄膜上除去形成在绝缘膜和栅电极交替层叠在一起的叠层膜的侧壁上的薄沟道半导体层时,包括沟道半导体层的垂直晶体管与栅电极之间的接触电阻, 并且防止形成在层叠膜上的位线上升。 作为其手段,电连接到沟道半导体层的导电层设置在堆叠膜的正上方。
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公开(公告)号:US08866123B2
公开(公告)日:2014-10-21
申请号:US13884331
申请日:2010-11-22
IPC分类号: H01L47/00 , H01L45/00 , H01L29/792 , H01L27/24 , H01L29/66 , H01L27/115
CPC分类号: H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
摘要翻译: 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管,它们是以矩阵形式排列的垂直晶体管,第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管,以及多个存储单元串联连接 双层选择晶体管。 利用这种配置,防止相邻的选择晶体管被相应的共享栅极选择,可以独立地选择多个两层选择晶体管,并且防止非易失性存储装置的存储容量减小。
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公开(公告)号:US08772746B2
公开(公告)日:2014-07-08
申请号:US13349653
申请日:2012-01-13
IPC分类号: H01L47/00
CPC分类号: H01L45/06 , H01L27/2454 , H01L27/2472 , H01L45/144 , H01L45/1675
摘要: A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.
摘要翻译: 可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。 在半导体存储器件中,连续地沿着Y方向延伸的多个字线形成栅极绝缘膜,沿X方向延伸的沟道和沿X方向延伸的电阻变化元件,并且沟道的一部分和 电阻变化元件的一部分设置在多条字线的上方。 这样的配置可以减小单元面积并确保设计自由度。
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公开(公告)号:US09153774B2
公开(公告)日:2015-10-06
申请号:US13884263
申请日:2010-12-06
申请人: Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
发明人: Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC分类号: H01L27/06 , H01L45/00 , H01L27/102 , H01L29/792 , H01L27/24 , H01L27/115 , G11C13/00
CPC分类号: H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
摘要: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.
摘要翻译: 当在叠层薄膜上除去形成在绝缘膜和栅电极交替层叠在一起的叠层膜的侧壁上的薄沟道半导体层时,包括沟道半导体层的垂直晶体管与栅电极之间的接触电阻, 并且防止形成在层叠膜上的位线上升。 作为其手段,电连接到沟道半导体层的导电层设置在堆叠膜的正上方。
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公开(公告)号:US20130234101A1
公开(公告)日:2013-09-12
申请号:US13884331
申请日:2010-11-22
IPC分类号: H01L45/00
CPC分类号: H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
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