公开(公告)号：US08541768B2

公开(公告)日：2013-09-24

申请号：US13118402

申请日：2011-05-28

申请人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

发明人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

IPC分类号： H01L29/02

CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

公开(公告)号：US08427865B2

公开(公告)日：2013-04-23

申请号：US13440225

申请日：2012-04-05

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US20120149143A1

公开(公告)日：2012-06-14

申请号：US13303227

申请日：2011-11-23

申请人： Keiji WATANABE ,  Toshiyuki MINE ,  Akio SHIMA ,  Tomoko SEKIGUCHI ,  Ryuta TSUCHIYA

发明人： Keiji WATANABE ,  Toshiyuki MINE ,  Akio SHIMA ,  Tomoko SEKIGUCHI ,  Ryuta TSUCHIYA

IPC分类号： H01L31/18

CPC分类号： H01L31/02168 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/055 ,  H01L31/075 ,  H01L31/1872 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。

公开(公告)号：US20120074368A1

公开(公告)日：2012-03-29

申请号：US13181663

申请日：2011-07-13

申请人： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Takashi KOBAYASHI

发明人： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Takashi KOBAYASHI

IPC分类号： H01L47/00 ,  H01L21/3205

CPC分类号： H01L27/2445 ,  H01L27/0688 ,  H01L27/1021 ,  H01L45/1226 ,  H01L45/144

摘要： A semiconductor memory device having a diode and a transistor connected in series, which prevents carriers from going from the diode into the transistor, thereby reducing the possibility of transistor deterioration. A structure to annihilate carriers from the diode is provided between a channel layer of the transistor and a diode semiconductor layer of the diode where the carriers are generated.

摘要翻译： 具有串联连接的二极管和晶体管的半导体存储器件，其防止载流子从二极管进入晶体管，从而降低晶体管劣化的可能性。 在晶体管的沟道层和二极管的二极管半导体层之间提供从二极管湮灭载流子的结构，其中产生载流子。

公开(公告)号：US20080145987A1

公开(公告)日：2008-06-19

申请号：US11943639

申请日：2007-11-21

申请人： Akio Shima

发明人： Akio Shima

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/8249 ,  H01L27/1052

摘要： A reflectance-controlling layer whose reflectance to irradiation of laser light becomes lower as a thickness thereof becomes thinner is formed on a semiconductor substrate having a first region and a second region. Thereafter, the reflectance-controlling layer on the first region is etched. Then, a laser light is irradiated to the semiconductor substrate to anneal an n−-type semiconductor region and an n+-type semiconductor region of the first region. In the same manner, after the reflectance-controlling layer is formed on the semiconductor substrate, the reflectance-controlling layer on the second region is etched. Then, a laser light is irradiated to the semiconductor substrate to anneal a p−-type semiconductor region and a p+-type semiconductor region of the second region.

摘要翻译： 在具有第一区域和第二区域的半导体衬底上形成反射率控制层，其反射率随着其厚度变薄而变低。 此后，蚀刻第一区域上的反射率控制层。 然后，将激光照射到半导体衬底上，以退火第一区域的n + O - 型半导体区域和n + + + / - 半导体区域。 以相同的方式，在半导体衬底上形成反射控制层之后，蚀刻第二区域上的反射控制层。 然后，将激光照射到半导体衬底上，以退火第二区域的p + / - 型半导体区域和p + + + / - 半导体区域。

公开(公告)号：US07174735B2

公开(公告)日：2007-02-13

申请号：US10764374

申请日：2004-01-22

申请人： Kouichi Satoh ,  Seiji Yanagisawa ,  Shu Watabe ,  Yukihiro Fujita ,  Akio Shima ,  Yuji Tanaka ,  Shinichi Takahashi ,  Hiroshi Kunii

发明人： Kouichi Satoh ,  Seiji Yanagisawa ,  Shu Watabe ,  Yukihiro Fujita ,  Akio Shima ,  Yuji Tanaka ,  Shinichi Takahashi ,  Hiroshi Kunii

IPC分类号： F25B27/00 ,  G05D23/00

CPC分类号： F24F5/0017 ,  Y02E10/22 ,  Y02E10/28 ,  Y02E60/147 ,  Y02E60/17 ,  Y02P70/525

摘要： In the air-conditioning system, a primary side to generate heat includes a heat storage and a heat source and produces cool or warm water using an inexpensive commercial power source such as a nighttime power source. A system collaboration unit is disposed between a motor to drive a water pump and a power source. The unit is connected to the motor via a cable. An output from the inverter is connected to the motor via a cable.

公开(公告)号：US08866123B2

公开(公告)日：2014-10-21

申请号：US13884331

申请日：2010-11-22

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Akio Shima ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Akio Shima ,  Takashi Kobayashi

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L29/792 ,  H01L27/24 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L27/2436 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1683

摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

摘要翻译： 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 双层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

公开(公告)号：US20130341729A1

公开(公告)日：2013-12-26

申请号：US13812181

申请日：2011-06-20

申请人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

发明人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

IPC分类号： H01L27/06

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C16/0408 ,  H01L21/8249 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/1025 ,  H01L27/1026 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1004 ,  H01L29/1033 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7311 ,  H01L29/788 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.

摘要翻译： 提供了与MOSFET相比具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /阶的优异的开关特性。 组合MOSFET和具有隧道结的隧道双极晶体管配置了一个半导体元件，其相对于栅极电压的变化（S值小于60mV /次）显示出漏极电流的突然变化，即使在 低电压。

公开(公告)号：US07906834B2

公开(公告)日：2011-03-15

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L23/552

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

公开(公告)号：US07191610B2

公开(公告)日：2007-03-20

申请号：US10822102

申请日：2004-04-08

申请人： Koichi Satoh ,  Seiji Yanagisawa ,  Shu Watabe ,  Yukihiro Fujita ,  Akio Shima ,  Yuji Tanaka ,  Shinichi Takahashi ,  Hiroshi Kunii

发明人： Koichi Satoh ,  Seiji Yanagisawa ,  Shu Watabe ,  Yukihiro Fujita ,  Akio Shima ,  Yuji Tanaka ,  Shinichi Takahashi ,  Hiroshi Kunii

IPC分类号： F25B27/00

CPC分类号： F24F5/0017 ,  Y02E10/22 ,  Y02E10/28 ,  Y02E60/147 ,  Y02E60/17 ,  Y02P70/525

摘要： In the air-conditioning system, a primary side to generate heat includes a heat storage and a heat source and produces cool or warm water using an inexpensive commercial power source such as a nighttime power source. A system collaboration unit is disposed between a motor to drive a water pump and a power source. The unit is connected to the motor via a cable. An output from the inverter is connected to the motor via a cable.

摘要翻译： 在空调系统中，产生热量的初级侧包括蓄热器和热源，并且使用诸如夜间电源的廉价的商业电源产生冷水或温水。 系统协作单元设置在驱动水泵和电源的马达之间。 本机通过电缆连接到电机。 逆变器的输出通过电缆连接到电机。