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    Semiconductor device having stacked structural bodies and method for manufacturing the same
    5.
    发明授权
    Semiconductor device having stacked structural bodies and method for manufacturing the same 有权
    具有层叠结构体的半导体装置及其制造方法

    公开(公告)号：US08541768B2

    公开(公告)日：2013-09-24

    申请号：US13118402

    申请日：2011-05-28

    申请人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

    发明人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

    摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

    摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110297911A1

    公开(公告)日：2011-12-08

    申请号：US13118402

    申请日：2011-05-28

    申请人： Akio SHIMA ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

    发明人： Akio SHIMA ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

    IPC分类号： H01L47/00

    CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

    摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

    摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

    Semiconductor memory device and manufacturing method of the same
    7.
    发明授权
    Semiconductor memory device and manufacturing method of the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US07969760B2

    公开(公告)日：2011-06-28

    申请号：US11790590

    申请日：2007-04-26

    申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    IPC分类号： G11C5/06

    CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

    摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

    Semiconductor memory device and manufacturing method of the same
    8.
    发明申请
    Semiconductor memory device and manufacturing method of the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20070285983A1

    公开(公告)日：2007-12-13

    申请号：US11790590

    申请日：2007-04-26

    申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    IPC分类号： G11C11/34 ,  H01L21/336

    CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

    摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20070257305A1

    公开(公告)日：2007-11-08

    申请号：US11740799

    申请日：2007-04-26

    申请人： Yoshitaka SASAGO ,  Tomoyuki Ishi ,  Toshiyuki Mine ,  Taro Osabe

    发明人： Yoshitaka SASAGO ,  Tomoyuki Ishi ,  Toshiyuki Mine ,  Taro Osabe

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11524

    摘要： By decreasing the threshold voltage shift due to the potential change of the cells adjacent in a word line direction, the reliability of a flash memory can be enhanced. Memory cells of a flash memory are formed in p-type wells of a semiconductor substrate and include gate insulator films, floating gates, high-K insulator films, and control gates (word lines). The floating gates and control gates (word lines) are isolated by high-K insulator films. The plurality of memory cells arrayed in row a direction are isolated by isolation trenches extending in a column direction. In the isolation trenches, a silicon oxide film is embedded. In the silicon oxide film, an air gap is provided. A lower end of the air gap extends near to the bottom of the isolation trench, and its upper end extends further above the upper surface of the high-K insulator film covering the floating gate.

    摘要翻译： 通过由于在字线方向上相邻的单元的电位变化而减小阈值电压偏移，可以提高闪速存储器的可靠性。 闪存的存储单元形成在半导体衬底的p型阱中，并且包括栅绝缘膜，浮栅，高K绝缘膜和控制栅（字线）。 浮动栅极和控制栅极（字线）由高K绝缘膜隔离。 沿着一个方向排列的多个存储单元通过沿列方向延伸的隔离沟槽隔离。 在隔离沟槽中，嵌入氧化硅膜。 在氧化硅膜中设置气隙。 气隙的下端部靠近隔离沟槽的底部延伸，并且其上端进一步延伸到覆盖浮动栅极的高K绝缘膜的上表面上方。

    Semiconductor memory device
    10.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20050173751A1

    公开(公告)日：2005-08-11

    申请号：US11002800

    申请日：2004-12-03

    申请人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Yoshitaka Sasago ,  Taro Osabe

    发明人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Yoshitaka Sasago ,  Taro Osabe

    IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L21/8239 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

    摘要： A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a plurality of assist gates are formed so as to be embedded in a p-type well via a silicon oxide film, respectively and silicon nanocrystal grains of about 6 nm in average diameter used for storing information are formed without being in contact with one another. Then, a plurality of word lines are formed practically in a direction vertically to the assist gates and the space between adjacent those of the plurality of word lines is set under ½ of the width (gate length) of the word lines. Consequently, the inversion layers formed at side faces of the assist gates will be used as local data lines, thereby the resistance is lowered and the writing characteristic variation among memory cells in a memory mat is suppressed.

    摘要翻译： 使用形成在其半导体衬底的表面上的反型层作为数据线的非易失性半导体存储器件，其能够满足抑制存储器单元之间的特性变化和位成本的要求。 为了实现上述目的，在存储装置中，分别形成多个辅助栅极，以分别通过氧化硅膜嵌入p型阱中，并使用平均直径约6nm的硅纳米晶粒 用于存储信息的形成而不彼此接触。 然后，在垂直于辅助栅极的方向上形成多个字线，并且将多个字线的相邻字线之间的空间设置在字线的宽度（栅极长度）的1/2以下。 因此，形成在辅助栅极的侧面的反转层将被用作本地数据线，从而电阻降低，并且抑制存储器垫中的存储单元之间的写入特性变化。