公开(公告)号：US06537870B1

公开(公告)日：2003-03-25

申请号：US09675432

申请日：2000-09-29

申请人： Hua Shen

发明人： Hua Shen

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10885

摘要： An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., 128, 228), and gate (e.g., 132, 232) of a DRAM cell may be formed using a minimal number of masks and lithographic steps. Using this process, a DRAM cell comprising a vertical transistor and a buried word line (e.g., 132, 232) may be formed. A gate dielectric (e.g., 130, 230) may be disposed adjacent the active area, and the portion of the buried word line adjacent the gate dielectric may function as the vertically oriented gate for the vertical transistor. The DRAM memory cell may comprise one of a variety of capacitors, such a trench capacitor underlying the vertical transistor, or a stack capacitor (e.g., 241) overlying the vertical transistor. When a stack capacitor is used, a buried bit line (e.g., 208) underlying the vertical transistor may also be used.

摘要翻译： 一种集成电路，其包括以基本上自适应处理形成的垂直取向的器件，其中DRAM单元的沟槽，有源区（例如，128,228）和栅极（例如，132,232）可以使用最小的 掩模数和光刻步骤。 使用该过程，可以形成包括垂直晶体管和掩埋字线（例如，132,232）的DRAM单元。 栅电介质（例如，130,230）可以邻近有源区设置，并且与栅极电介质相邻的掩埋字线的部分可以用作垂直晶体管的垂直取向的栅极。 DRAM存储单元可以包括各种电容器中的一个，垂直晶体管下面的这种沟槽电容器，或叠加在垂直晶体管上的堆叠电容器（例如241）。 当使用堆叠电容器时，也可以使用垂直晶体管下面的掩埋位线（例如208）。

公开(公告)号：US20060047710A1

公开(公告)日：2006-03-02

申请号：US11213146

申请日：2005-08-25

申请人： Jiong Hu ,  Hua Shen ,  Kai Wei

发明人： Jiong Hu ,  Hua Shen ,  Kai Wei

IPC分类号： G06F17/30

CPC分类号： G06F16/20

摘要： A globalized database method for accessing a globalized database system determines a locale identification from an application. A database stores a globalized database table that comprises a globalized column corresponding to a user query. Each of the globalized columns comprises data values related to different locales. A database access driver intercepts a database query command of the user. Based on the retrieved locale identification, the present method retrieves the locale sensitive data value corresponding to the locale identification from the globalized columns in the globalized database table.

摘要翻译： 用于访问全局化数据库系统的全局化数据库方法从应用程序确定区域设置标识。 数据库存储包含与用户查询对应的全球化列的全局化数据库表。 每个全局化列都包含与不同区域设置相关的数据值。 数据库访问驱动程序拦截用户的数据库查询命令。 基于检索到的区域设置识别，本方法从全局化数据库表中的全局化列中检索对应于区域设置标识的区域设置敏感数据值。

公开(公告)号：US6165864A

公开(公告)日：2000-12-26

申请号：US123298

申请日：1998-07-28

申请人： Hua Shen ,  Joachim Nuetzel ,  Carl J. Radens ,  David Kotecki

发明人： Hua Shen ,  Joachim Nuetzel ,  Carl J. Radens ,  David Kotecki

IPC分类号： H01G4/12 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： A method for forming a stacked capacitor includes the steps of providing a first insulating layer having a conductive access path therethrough, forming a second insulating layer on the first insulating layer, forming a trench in the second insulating layer, the trench having tapered sidewalls, forming a first electrode in the trench and on the trench sidewalls, the first electrode being electrically coupled to the conductive access path, forming a dielectric layer on the first electrode and forming a second electrode on the dielectric layer. A stacked capacitor having increased surface area includes a first electrode formed in a trench provided in a dielectric material. The first electrode has tapered surfaces forming a conically shaped portion of the first electrode, the first electrode for accessing a capacitively coupled storage node.

摘要翻译： 一种叠层电容器的形成方法包括以下步骤：提供具有导电通路的第一绝缘层，在第一绝缘层上形成第二绝缘层，在第二绝缘层中形成沟槽，沟槽具有锥形侧壁，形成 所述沟槽中的第一电极和所述沟槽侧壁上的第一电极，所述第一电极电耦合到所述导电接入路径，在所述第一电极上形成电介质层，并在所述电介质层上形成第二电极。 具有增加的表面积的堆叠电容器包括形成在设置在电介质材料中的沟槽中的第一电极。 第一电极具有形成第一电极的锥形部分的锥形表面，用于访问电容耦合存储节点的第一电极。

公开(公告)号：US6046059A

公开(公告)日：2000-04-04

申请号：US074882

申请日：1998-05-08

申请人： Hua Shen ,  Joachim Hoepfner

发明人： Hua Shen ,  Joachim Hoepfner

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01G7/06

CPC分类号： H01L27/10852 ,  H01L28/60 ,  H01L29/94 ,  H01L28/55

摘要： The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

摘要翻译： 本发明包括一种改善层间电容器中电极和插塞之间的导电性的方法，其中形成氧化物。 该方法包括用离子轰击氧化物并将氧化物与电极和塞子的材料混合以增加电极和插塞之间的导电性的步骤。 在层叠电容器中在电极内形成扩散阻挡层的方法包括以下步骤：提供具有耦合到电极的插塞并用离子轰击电极的堆叠电容器，以在电极内形成扩散阻挡层，使得扩散阻挡层电 导电。 根据本发明的层叠电容器包括电极，用于电存取存储节点的插头，插头与电极耦合，以及设置在电极内的阻挡层，用于防止在电极和电极之间降低导电性的材料扩散 插头。

公开(公告)号：US6001684A

公开(公告)日：1999-12-14

申请号：US868555

申请日：1997-06-04

申请人： Hua Shen

发明人： Hua Shen

IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L29/66181 ,  H01L27/10829 ,  H01L29/945

摘要： A method for forming a capacitor in a semiconductor body is provided. The method includes the step of forming a trench in a portion of a surface of the semiconductor body. The trench having sidewalls and a bottom. A doped film is deposited over the surface of the semiconductor body. Portions of the doped film are deposited over the sidewalls and bottom of the trench. The semiconductor body is heated and the doped film to produce a liquid phase interface region therebetween while diffusing dopant in the doped film into a region of the semiconductor body. The interface region is cooled to return such interface region to a solid phase. The doped film and the interface region are removed from the semiconductor body while leaving the doped region in the semiconductor body. A dielectric film is deposited over the doped region of the semiconductor body. A doped material is deposited over the dielectric film, the doped material and the doped region in the semiconductor body providing electrodes for the capacitor and the dielectric film providing a dielectric for the capacitor. The heating and cooling steps comprise the steps of: subjecting the semiconductor body and doped film to an energized source of radiant heat to heat such body and doped film and subsequently de-energizing the energized source of radiant heat to cool the doped semiconductor body and doped film. The cooling is at a rate sufficiently rapid to avoid formation of silicon arsenic precipitate.

摘要翻译： 提供一种在半导体本体中形成电容器的方法。 该方法包括在半导体本体的表面的一部分中形成沟槽的步骤。 沟槽具有侧壁和底部。 掺杂的膜沉积在半导体本体的表面上。 掺杂膜的一部分沉积在沟槽的侧壁和底部上。 加热半导体体和掺杂膜以在其间产生液相界面区，同时将掺杂膜中的掺杂剂扩散到半导体本体的区域。 界面区域被冷却以将这种界面区域返回到固相。 在半导体本体中留下掺杂区域的同时，从半导体本体去除掺杂膜和界面区域。 电介质膜沉积在半导体本体的掺杂区域上。 掺杂材料沉积在电介质膜上，掺杂材料和半导体本体中的掺杂区域为电容器提供电极和为电容器提供电介质的电介质膜。 加热和冷却步骤包括以下步骤：将半导体主体和掺杂膜经受辐射热的激励源以加热该体和掺杂膜，随后使激发的辐射热源断电以冷却掺杂的半导体主体并掺杂 电影。 冷却速度足够快以避免形成硅砷沉淀物。

公开(公告)号：US06621325B2

公开(公告)日：2003-09-16

申请号：US09956203

申请日：2001-09-18

申请人： Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

发明人： Michael J. Hart ,  Steven P. Young ,  Daniel Gitlin ,  Hua Shen ,  Stephen M. Trimberger

IPC分类号： H03K301

CPC分类号： H03K19/17792 ,  G06F17/5054 ,  H01L27/0928 ,  H01L27/11807

摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

摘要翻译： 用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。 用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。 在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。 在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

公开(公告)号：US06313495B1

公开(公告)日：2001-11-06

申请号：US09478312

申请日：2000-01-06

申请人： Hua Shen ,  Joachim Hoepfner

发明人： Hua Shen ,  Joachim Hoepfner

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/60 ,  H01L29/94

摘要： The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

摘要翻译： 本发明包括一种改善层间电容器中的电极和插塞之间的导电性的方法，其中形成氧化物。 该方法包括用离子轰击氧化物并将氧化物与电极和插塞的材料混合以增加电极和插塞之间的导电性的步骤。 在层叠电容器中在电极内形成扩散阻挡层的方法包括以下步骤：提供具有耦合到电极的插塞并用离子轰击电极的堆叠电容器，以在电极内形成扩散阻挡层，使得扩散阻挡层电 导电。 根据本发明的层叠电容器包括电极，用于电存取存储节点的插头，插头与电极耦合，以及设置在电极内的阻挡层，用于防止在电极和电极之间降低导电性的材料扩散 插头。

公开(公告)号：US6136660A

公开(公告)日：2000-10-24

申请号：US161861

申请日：1998-09-28

申请人： Hua Shen ,  Gerhard Kunkel ,  Martin Gutsche

发明人： Hua Shen ,  Gerhard Kunkel ,  Martin Gutsche

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/60 ,  H01L27/10855

摘要： A memory cell includes a field effect transistor and a stacked capacitor. The stacked capacitor has one plate formed by a platinum layer over the side walls of a portion of a dielectric layer that overlies a conductive layer that makes contact to a conductive plug connected to the storage node of the cell. The capacitor dielectric overlies the sidewalls and top of the dielectric layer portion and the other plate of the capacitor is formed by a platinum layer over the capacitor dielectric.

摘要翻译： 存储单元包括场效应晶体管和层叠电容器。 叠层电容器具有由介电层的一部分的侧壁上的铂层形成的一个板，所述介电层的一部分覆盖导电层，该导电层与连接到电池的存储节点的导电插塞接触。 电容器电介质覆盖在电介质层部分的侧壁和顶部，电容器的另一个电极由电容器电介质上的铂层形成。

公开(公告)号：US5966624A

公开(公告)日：1999-10-12

申请号：US901986

申请日：1997-07-29

申请人： Hua Shen

发明人： Hua Shen

IPC分类号： H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/20

CPC分类号： H01L21/0217 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31612

摘要： A structure for semiconductors having a crystalline layer includes a first silicon-containing dielectric film formed on a semiconductor substrate. A crystalline layer is formed on the first dielectric film by hydrogen annealing the surface of the first dielectric layer to form a layer of silicon atoms. The silicon atoms are reacted with a gas containing nitrogen or annealed in the presence of an inert gas to form either a crystalline layer of silicon nitride or a crystalline layer of silicon, respectively. A second dielectric film can be formed on the crystalline layer. In particularly useful embodiments, the crystalline layer of silicon or silicon nitride is three to twenty monolayers. The silicon nitride structure described herein forms an improved dielectric structure reducing the thickness of dielectric layer and improving resistance to electrical breakdown. The silicon structure described herein forms a semiconductor layer on a dielectric layer.

摘要翻译： 具有结晶层的半导体结构包括在半导体衬底上形成的第一含硅电介质膜。 通过对第一介电层的表面进行氢退火以形成硅原子层，在第一介电膜上形成结晶层。 硅原子与含氮气体反应或在惰性气体存在下进行退火，分别形成氮化硅结晶层或硅晶体层。 可以在晶体层上形成第二电介质膜。 在特别有用的实施方案中，硅或氮化硅的晶体层为三至二十个单层。 本文所述的氮化硅结构形成了改善的电介质结构，减小了电介质层的厚度并提高了电击穿的能力。 本文所述的硅结构在电介质层上形成半导体层。