公开(公告)号：US06313495B1

公开(公告)日：2001-11-06

申请号：US09478312

申请日：2000-01-06

申请人： Hua Shen ,  Joachim Hoepfner

发明人： Hua Shen ,  Joachim Hoepfner

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/60 ,  H01L29/94

摘要： The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

摘要翻译： 本发明包括一种改善层间电容器中的电极和插塞之间的导电性的方法，其中形成氧化物。 该方法包括用离子轰击氧化物并将氧化物与电极和插塞的材料混合以增加电极和插塞之间的导电性的步骤。 在层叠电容器中在电极内形成扩散阻挡层的方法包括以下步骤：提供具有耦合到电极的插塞并用离子轰击电极的堆叠电容器，以在电极内形成扩散阻挡层，使得扩散阻挡层电 导电。 根据本发明的层叠电容器包括电极，用于电存取存储节点的插头，插头与电极耦合，以及设置在电极内的阻挡层，用于防止在电极和电极之间降低导电性的材料扩散 插头。

公开(公告)号：US6046059A

公开(公告)日：2000-04-04

申请号：US074882

申请日：1998-05-08

申请人： Hua Shen ,  Joachim Hoepfner

发明人： Hua Shen ,  Joachim Hoepfner

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01G7/06

CPC分类号： H01L27/10852 ,  H01L28/60 ,  H01L29/94 ,  H01L28/55

摘要： The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

摘要翻译： 本发明包括一种改善层间电容器中电极和插塞之间的导电性的方法，其中形成氧化物。 该方法包括用离子轰击氧化物并将氧化物与电极和塞子的材料混合以增加电极和插塞之间的导电性的步骤。 在层叠电容器中在电极内形成扩散阻挡层的方法包括以下步骤：提供具有耦合到电极的插塞并用离子轰击电极的堆叠电容器，以在电极内形成扩散阻挡层，使得扩散阻挡层电 导电。 根据本发明的层叠电容器包括电极，用于电存取存储节点的插头，插头与电极耦合，以及设置在电极内的阻挡层，用于防止在电极和电极之间降低导电性的材料扩散 插头。

公开(公告)号：US06465370B1

公开(公告)日：2002-10-15

申请号：US09105633

申请日：1998-06-26

申请人： Martin Schrems ,  Rolf-Peter Vollertsen ,  Joachim Hoepfner

发明人： Martin Schrems ,  Rolf-Peter Vollertsen ,  Joachim Hoepfner

IPC分类号： H01L21469

CPC分类号： H01L27/10861 ,  H01L21/3003 ,  H01L29/66181 ,  H01L2924/0002 ,  Y10S438/918 ,  H01L2924/00

摘要： A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method includes the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen includes forming hydrogen atoms in the surface with concentrations of 1017 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are introduced by baking in hydrogen at a temperature of 950° C. to 1100° C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.

摘要翻译： 减少形成在硅衬底上的电容的方法包括将氢原子引入所述表面的一部分以增加表面部分的介电常数增加介电材料的有效厚度从而减小所述电容的步骤。 该方法包括形成厚度大于2纳米的二氧化硅层的步骤。 引入氢的步骤包括在表面上形成浓度为1017原子/立方厘米或更大的氢原子。 在一个实施方案中，氢原子通过在氢气中在950℃至1100℃的温度和大于100托的压力下进行烘烤而引入。 提供了一种沟槽电容器DRAM单元，其中氢提供钝化层以增加环绕区域周围的有效电容，从而减少不需要的晶体管作用。

公开(公告)号：US5945704A

公开(公告)日：1999-08-31

申请号：US105945

申请日：1998-06-26

申请人： Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

发明人： Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119 ,  H01L27/76

CPC分类号： H01L27/10861 ,  H01L29/945

摘要： A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

摘要翻译： 具有沟槽下部的外延层的沟槽式电容器。 外延层用作沟槽电容器的掩埋板。 扩散区域围绕沟槽的下部以增强外延层的掺杂剂浓度。 扩散区域通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。

公开(公告)号：US5057668A

公开(公告)日：1991-10-15

申请号：US232237

申请日：1988-08-15

申请人： Spyridon Gisdakis ,  Joachim Hoepfner

发明人： Spyridon Gisdakis ,  Joachim Hoepfner

IPC分类号： H01L21/265 ,  C30B31/12 ,  C30B33/00 ,  H01L21/26 ,  H01L21/324

CPC分类号： C30B33/00 ,  C30B31/12

摘要： In an apparatus for curing semiconductor wafers implementing same is provided. Pursuant to the method, semiconductor wafers, for example, GaAs, are cured in a reaction tube under a protective gas atmosphere of, for example, a mixture of N.sub.2 and AsH.sub.3. The reaction tube is initially heated to a base temperature at which the curing process is not initiated and at which no wall coatings occur. Given semiconductor wafers of compound semiconductors such as, for axample, GaAs, the protective atmosphere contains a compound of the more volatile element, for example, AsH.sub.3, that decomposes at the base temperature and forms an over-pressure of the more volatile element. The semiconductor wafer is heated to the curing temperature with a selective heater, for example a lamp, and is exposed to the curing temperature for 5 through 20 seconds.

摘要翻译： 提供了一种用于固化实现其的半导体晶片的固化装置。 根据该方法，半导体晶片（例如GaAs）在例如N 2和AsH 3的混合物的保护气体气氛下在反应管中固化。 反应管最初被加热到基本温度，在该温度下固化过程不被引发，并且没有发生壁涂层。 给出化合物半导体的半导体晶片，例如对于GaAs，保护气氛包含更易挥发的元素，例如AsH 3的化合物，其在基本温度下分解并形成更易挥发的元素的过压。 用选择性加热器（例如灯）将半导体晶片加热至固化温度，并暴露于固化温度5至20秒。

公开(公告)号：US06645855B2

公开(公告)日：2003-11-11

申请号：US09995210

申请日：2001-11-27

申请人： Joachim Hoepfner

发明人： Joachim Hoepfner

IPC分类号： H01L2144

CPC分类号： H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one connection, in particular a polysilicon connection. The next step is exposing the at least one connection from the wafer front surface. The next step is applying a protective layer, in particular a silicon nitride protective layer, to the wafer front surface. The next step is treating the wafer front surface by a chemical mechanical polishing (CMP) step, with the result that the at least one connection is made accessible again.

公开(公告)号：US4092210A

公开(公告)日：1978-05-30

申请号：US705785

申请日：1976-07-16

申请人： Joachim Hoepfner

发明人： Joachim Hoepfner

IPC分类号： C23F4/00 ,  C23F1/00 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  C23F1/02

CPC分类号： H01L21/31105 ,  H01L21/0335 ,  H01L21/31144

摘要： A process for producing an etched structure in a surface of a solid body by providing a mask on the surface of the solid body to expose the desired portions of the surface, ionic etching the mask and the exposed surface with the material of the mask and the material of the solid body being disintegrated and removed by the ion bombardment of the ionic etching characterized by the disintegration rate of the mask being changed during the ionic etching step. In one embodiment of the process the mask is composed of at least two layers having different disintegration rates with the layer having the highest disintegration rate being disposed adjacent the surface and the layer with the lower disintegration being disposed thereon. In another embodiment of the invention, the mask comprises a single layer of material, such as metal, and the rate of disintegration of the masking layer is changed by adding a reactive gas during a portion of the ionic etching step.

摘要翻译： 一种通过在固体的表面上提供掩模以暴露表面的所需部分以形成掩模的表面的蚀刻结构的方法，用掩模的材料离子蚀刻掩模和暴露的表面， 通过离子蚀刻的离子轰击将固体的材料分解和去除，其特征在于在离子蚀刻步骤期间改变掩模的崩解速率。 在该方法的一个实施方案中，掩模由具有不同崩解速率的至少两层组成，具有最高崩解速率的层被设置为邻近表面，并且具有较低崩解层的层被设置在其上。 在本发明的另一实施例中，掩模包括单层材料，例如金属，并且通过在离子蚀刻步骤的一部分期间添加反应性气体来改变掩模层的崩解速率。

公开(公告)号：US06475859B1

公开(公告)日：2002-11-05

申请号：US09593287

申请日：2000-06-13

申请人： Helmut Horst Tews ,  Brian S. Lee ,  Joachim Hoepfner

发明人： Helmut Horst Tews ,  Brian S. Lee ,  Joachim Hoepfner

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/2236 ,  H01L28/84

摘要： A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG-Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

摘要翻译： 一种在深沟槽单元中掺杂沟槽侧壁和半球晶硅的方法，以增加表面面积和存储电容，同时避免沟槽和半球晶硅的变形，包括：a）通过反应离子蚀刻蚀刻深沟槽结构; b）形成 在包含硅的材料的保形层上的沟槽上部的LOCOS环，所述套环暴露出沟槽的下部; c）在半导体衬底的侧壁处沉积半球形硅（HSG-Si）的膜 深沟槽; d）等离子体掺杂半球形硅; 安装）沉积节点电介质并用多晶硅填充沟槽。

公开(公告)号：US6008103A

公开(公告)日：1999-12-28

申请号：US31995

申请日：1998-02-27

申请人： Joachim Hoepfner

发明人： Joachim Hoepfner

IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10861 ,  H01L29/66181

摘要： A method for forming a trench capacitor in a substrate, including a buried plate of the trench capacitor, is disclosed. The method includes forming a trench within the substrate. The trench has a trench interior surface. The method further includes forming an oxide collar within the trench. The oxide collar covers a first portion of the trench interior surface, leaving a second portion of the trench interior surface uncovered with the oxide collar. There is also included doping the second portion of the trench interior surface with a first dopant using a plasma-enhanced doping process. The plasma-enhanced doping process being configured to cause the first dopant to diffuse into the second portion substantially without depositing an additional layer on the trench interior surface. Additionally, there is included driving the first dopant into the substrate using a high temperature process to form the buried plate.

摘要翻译： 公开了一种在包括沟槽电容器的掩埋板的衬底中形成沟槽电容器的方法。 该方法包括在衬底内形成沟槽。 沟槽具有沟槽内表面。 该方法还包括在沟槽内形成氧化物环。 氧化物套环覆盖沟槽内表面的第一部分，留下沟槽内表面的第二部分未被氧化物套环覆盖。 还包括使用等离子体增强掺杂工艺用第一掺杂剂掺杂沟槽内表面的第二部分。 等离子体增强掺杂工艺被配置为使得第一掺杂剂基本上不扩散到第二部分中，而不在沟槽内表面上沉积附加层。 此外，包括使用高温处理将第一掺杂剂驱动到衬底中以形成掩埋板。

公开(公告)号：US5340755A

公开(公告)日：1994-08-23

申请号：US912271

申请日：1992-10-13

申请人： Hans-Peter Zwicknagl ,  Joachim Hoepfner ,  Lothar Schleicher

发明人： Hans-Peter Zwicknagl ,  Joachim Hoepfner ,  Lothar Schleicher

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L29/737 ,  H01L21/265 ,  H01L29/70

CPC分类号： H01L29/66318 ,  H01L21/28 ,  H01L29/7371 ,  Y10S148/072

摘要： A planar heterobipolar transistor and its methods for manufacture provide that the transistor has the base-emitter region separated from the collector terminal by a collector parting trench and the parting trench structure may be used to separate the transistor from adjoining function components.

摘要翻译： 平面异质双极晶体管及其制造方法提供晶体管具有通过集电极分离沟槽与集电极端子分离的基极 - 发射极区域，并且分离沟槽结构可用于将晶体管与相邻的功能部件分离。