公开(公告)号：US07202118B1

公开(公告)日：2007-04-10

申请号：US10460402

申请日：2003-06-13

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66636 ,  H01L29/66772

摘要： A fully depleted SOI MOSFET arrangement includes a buried oxide (BOX) layer with recesses in the BOX layer and a post extended upwardly between the recesses. A thin channel region is formed on the post and a gate over the channel. Deep source/drain region are adjacent to the channel region and extend into the recesses.

摘要翻译： 完全耗尽的SOI MOSFET布置包括在BOX层中具有凹陷的掩埋氧化物（BOX）层和在凹部之间向上延伸的柱。 在通道上形成了一个薄的通道区域和一个栅极。 深源极/漏极区域与沟道区域相邻并延伸到凹槽中。

公开(公告)号：US06975014B1

公开(公告)日：2005-12-13

申请号：US09826634

申请日：2001-04-05

申请人： Zoran Krivokapic ,  Sunny Cherian ,  Allison Holbrook

发明人： Zoran Krivokapic ,  Sunny Cherian ,  Allison Holbrook

IPC分类号： H01L21/336 ,  H01L29/00 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78621

摘要： A method for forming a FDSOI device with channel length less than 50 nm with good short channel control. The gate has a tapered polysilicon spacer and a dielectric spacer. A polysilicon gate feature is formed and dielectric sidewall spacers are formed thereon. The polysilicon gate feature is then etched to form tapered poly features separated by a gap. A gate dielectric is deposited at low temperature, then metal is deposited into the gap to form the metal gate.

摘要翻译： 用于形成通道长度小于50nm并具有良好的短通道控制的FDSOI器件的方法。 栅极具有锥形多晶硅间隔物和电介质间隔物。 形成多晶硅栅极特征，并在其上形成电介质侧壁间隔物。 然后蚀刻多晶硅栅极特征以形成由间隙分开的锥形多晶硅特征。 在低温下沉积栅极电介质，然后将金属沉积到间隙中以形成金属栅极。

公开(公告)号：US06917068B1

公开(公告)日：2005-07-12

申请号：US10454517

申请日：2003-06-05

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L29/42332 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42384 ,  H01L29/4983 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/7883

摘要： A semiconductor device is provided by forming a gate electrode and a dielectric layer below and adjacent the side surfaces of the gate electrode. Relatively thin conductive structures are formed within the dielectric layer. The conductive structures may be used as a floating gate electrode for a memory device. The conductive structures may also be used to control a threshold voltage for a logic device.

摘要翻译： 通过在栅电极的侧表面下方和邻近形成栅电极和电介质层来提供半导体器件。 在介电层内形成相对较薄的导电结构。 导电结构可以用作存储器件的浮栅电极。 导电结构也可用于控制逻辑器件的阈值电压。

公开(公告)号：US06897527B2

公开(公告)日：2005-05-24

申请号：US10833112

申请日：2004-04-28

申请人： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

发明人： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.

摘要翻译： 半导体器件包括翅片和形成在鳍片的至少一部分上的层。 翅片包括第一结晶材料。 该层包括第二结晶材料，其中第一结晶材料具有比第二结晶材料更大的晶格常数以在层内引起拉伸应变。

公开(公告)号：US06861307B2

公开(公告)日：2005-03-01

申请号：US10631199

申请日：2003-07-31

申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/8238

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

摘要翻译： 在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。 该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层 势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。 去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

公开(公告)号：US06855583B1

公开(公告)日：2005-02-15

申请号：US10633503

申请日：2003-08-05

申请人： Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

发明人： Zoran Krivokapic ,  Judy Xilin An ,  Bin Yu

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795

摘要： A method forming a tri-gate fin field effect transistor includes forming an oxide layer over a silicon-on-insulator wafer comprising a silicon layer, and etching the silicon and oxide layers using a rectangular mask to form a mesa. The method further includes etching a portion of the mesa using a second mask to form a fin, forming a gate dielectric layer over the fin, and forming a tri-gate over the fin and the gate dielectric layer.

摘要翻译： 形成三栅极鳍场效应晶体管的方法包括在包括硅层的绝缘体上硅晶片上形成氧化物层，并且使用矩形掩模蚀刻硅和氧化物层以形成台面。 该方法还包括使用第二掩模蚀刻台面的一部分以形成翅片，在翅片上形成栅极电介质层，并在鳍状物和栅极介电层上形成三栅极。

公开(公告)号：US06762483B1

公开(公告)日：2004-07-13

申请号：US10348910

申请日：2003-01-23

申请人： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

发明人： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L2906

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

摘要翻译： 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06727546B2

公开(公告)日：2004-04-27

申请号：US10379239

申请日：2003-03-03

申请人： Zoran Krivokapic ,  Matthew Buynoski

发明人： Zoran Krivokapic ,  Matthew Buynoski

IPC分类号： H01L2976

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region. Also disclosed is a method for manufacturing a transistor device. The method for manufacturing includes the steps of: providing a substrate having a buried oxide region; depositing a first nitride mask layer having a pattern overlying a silicon region; forming a trench in said substrate with a depth to said buried oxide; depositing a conformal oxide in said trench; forming vias in said conformal oxide adjacent to said silicon region and removing a portion of said first nitride mask to expose a portion of said silicon region; depositing polysilicon in said vias and on said portion of said silicon region; and implanting an impurity into exposed portions of polysilicon in said trench and of said silicon-on-insulator substrate underlying said second nitride layer.

摘要翻译： 一种自对准晶体管，其包括在隔离层上的第一硅部分，所述硅部分在其中形成有源极区域和由沟道区域分开的漏极区域。 沟道区具有第一侧和第二侧以及顶部，栅极氧化物围绕所述第一侧，第二侧和顶部的沟道。 第一，第二和第三硅栅极区域围绕第一硅部分围绕第一侧面，第二侧面和顶部部分以及沟道区域定位在第二硅部分中。 还公开了一种用于制造晶体管器件的方法。 制造方法包括以下步骤：提供具有掩埋氧化物区域的衬底; 沉积具有覆盖硅区域的图案的第一氮化物掩模层; 在所述衬底中形成具有所述掩埋氧化物的深度的沟槽; 在所述沟槽中沉积保形氧化物; 在与所述硅区相邻的所述保形氧化物中形成通孔，并去除所述第一氮化物掩模的一部分以暴露所述硅区的一部分; 在所述通孔和所述硅区域的所述部分上沉积多晶硅; 以及将杂质注入所述沟槽中的多晶硅的暴露部分和所述第二氮化物层下面的所述绝缘体上硅衬底。

公开(公告)号：US06657276B1

公开(公告)日：2003-12-02

申请号：US10163925

申请日：2002-06-06

申请人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

发明人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC分类号： H01L2900

CPC分类号： H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

摘要翻译： 形成在半导体材料层中的浅沟槽隔离区。 浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。 还公开了形成浅沟槽隔离区域的方法。

公开(公告)号：US06555879B1

公开(公告)日：2003-04-29

申请号：US10044247

申请日：2002-01-11

申请人： Zoran Krivokapic ,  Qi Xiang ,  Bin Yu

发明人： Zoran Krivokapic ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L2976

CPC分类号： H01L21/28194 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.

摘要翻译： 一种MOSFET及其制造方法。 MOSFET包括含金属源和含金属的漏极; 设置在源极和漏极之间并且在绝缘层的顶部上具有小于约15nm的厚度的半导体本体，所述绝缘层形成在基板上; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。