公开(公告)号：US09753883B2

公开(公告)日：2017-09-05

申请号：US14172844

申请日：2014-02-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F12/10 ,  G06F13/42 ,  H04L12/741 ,  G06F9/455 ,  G06F21/53 ,  G06F21/85

CPC classification number: G06F13/4234 ,  G06F9/45558 ,  G06F12/10 ,  G06F21/53 ,  G06F21/85 ,  G06F2009/45595 ,  H04L45/74

Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. A virtual NID is configured by configuration information in an appropriate one of a set of smaller blocks in a high-speed memory on the NID. There is a smaller block for each virtual NID. A virtual machine on the host can configure its virtual NID by writing configuration information into a larger block in PCIe address space. Circuitry on the NID detects that the PCIe write is into address space occupied by the larger blocks. If the write is into this space, then address translation circuitry converts the PCIe address into a smaller address that maps to the appropriate one of the smaller blocks associated with the virtual NID to be configured. If the PCIe write is detected not to be an access of a larger block, then the NID does not perform the address translation.

公开(公告)号：US09753710B2

公开(公告)日：2017-09-05

申请号：US14074632

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Espen Skoglund ,  Rolf Neugebauer ,  Francois Henri Theron ,  Gavin J. Stark

IPC: G06F9/445 ,  G06F9/45

CPC classification number: G06F8/54 ,  G06F8/447

Abstract: A source code symbol can be declared to have a scope level indicative of a level in a hierarchy of scope levels, where the scope level indicates a circuit level or a sub-circuit level in the hierarchy. A novel instruction to the linker can define the symbol to be of a desired scope level. Location information indicates where different amounts of the object code are to be loaded into a system. A novel linker program uses the location information, along with the scope level information of the symbol, to uniquify instances of the symbol if necessary to resolve name collisions of symbols having the same scope. After the symbol uniquification step, the linker performs resource allocation. A resource instance is allocated to each symbol. The linker then replaces each instance of the symbol in the object code with the address of the allocated resource instance, thereby generating executable code.

公开(公告)号：US09678891B2

公开(公告)日：2017-06-13

申请号：US14326372

申请日：2014-07-08

Applicant: Netronome Systems, Inc.

Inventor： Rick Bouley

IPC: G06F13/00 ,  G06F12/1081 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/1081 ,  G06F13/28 ,  G06F13/4221 ,  G06F2212/2532

Abstract: A device includes a Standard Bus Interface Circuit (SBIC), a memory interface circuit, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. A search key data set including multiple search keys is received via the SBIC and is written to an external memory via the memory interface circuit. The DMA controller receives a descriptor via the SBIC, generates a search key data request, receives the search key data set, and selects a single search key from the set. The ILA interface circuit receives the search key from the DMA controller, generates and ILA packet including the search key, and sends the ILA packet to an external transactional memory device that generates a result data value. The DMA controller receives the result data value via the ILA interface circuit, writes the result data value to the external memory, and sends a DMA completion notification.

公开(公告)号：US09612841B1

公开(公告)日：2017-04-04

申请号：US14530765

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/30047 ,  G06F9/30069 ,  G06F9/383 ,  G06F9/46

Abstract: A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each of the processors has an intelligent packet data register file. One processor is tasked with processing the packet data, and its packet data register file caches a subset of the bytes. Some instructions when executed require that the packet data register file supply the processor execute stage with certain bytes of the packet data. The register file includes a set of slice portions, where each slice portion is responsible for different bytes of the overall packet data. Each slice portion independently handles stalling the processor and prefetching any bytes it is responsible for. The slice portions output their bytes in a shifted and masked fashion to that the overall register file output is properly presented to the execute stage.

公开(公告)号：US09558224B2

公开(公告)日：2017-01-31

申请号：US14151643

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F17/30

CPC classification number: G06F17/30339 ,  G06F17/30985

Abstract: An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most one n-bit entry value. Each row corresponds to an automaton state. In one example, at least two NFAs are encoded into the table. The first NFA is indexed into the rows of the transition table in a first way, and the second NFA is indexed in to the rows of the transition table in a second way. Due to this indexing, all rows are usable to store entry values that point to other rows.

Abstract translation: 自动机硬件引擎采用组织成2n行的转换表，其中每行包括多个n位存储位置，并且其中每个存储位置最多可以存储一个n位输入值。 每行对应于自动机状态。 在一个示例中，至少两个NFA被编码到表中。 第一个NFA以第一种方式索引到转换表的行中，第二个NFA以第二种方式索引到转换表的行中。 由于此索引，所有行都可用于存储指向其他行的条目值。

公开(公告)号：US09537801B1

公开(公告)日：2017-01-03

申请号：US14611224

申请日：2015-01-31

Applicant: Netronome Systems, Inc.

Inventor： Christopher A. Telfer ,  Jan Christoffel du Toit

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/863 ,  H04L12/859

CPC classification number: H04L49/9057 ,  G06F9/52 ,  H04L47/2475 ,  H04L47/625 ,  H04L49/109 ,  H04L69/22

Abstract: An Island-Based Network Flow Processor (IB-NFP) receives packets of many flows, and classifies each packet as belonging to one of a plurality of ordering contexts. As packets of an ordering context flow through the IB-NFP they are distributed to a set of Worker Processors (WPs). Each packet is processed by one WP, but multiple WPs are typically operating on packets of the ordering context at the same time. The ordering system handles releasing packets from the WPs to set of Output Processors (OP) in the correct order, even though WPs may complete their processing in an out-of-order fashion. One OP is responsible for generating “transmit commands” for packets of the ordering context. This OP generates a transmit command in the correct format as required by the particular egress destination circuit through which the packet will exit the IB-NFP. This architecture reduces code space, and facilitates good usage of processing resources.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）接收许多流的分组，并且将每个分组归类为属于多个排序上下文之一。 随着排序上下文的数据包流经IB-NFP，它们被分发给一组工作者处理器（WP）。 每个分组由一个WP处理，但是多个WP通常同时在排序上下文的分组上操作。 订购系统处理将WP中的数据包从正确的顺序发送到输出处理器（OP）的集合，即使WP可能以无序的方式完成其处理。 一个OP负责为排序上下文的数据包生成“传送命令”。 该OP按照特定出口目的地电路所要求的正确格式生成发送命令，通过该电路，数据包将通过该电路退出IB-NFP。 这种架构减少了代码空间，并且有利于处理资源的良好使用。

公开(公告)号：US09503372B1

公开(公告)日：2016-11-22

申请号：US14634851

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L49/25 ,  H04L49/351

Abstract: An integrated circuit includes ingress ethernet ports and egress ethernet ports. A second ingress ethernet port is configurable to operate in a selected one of a command mode and a data mode. The ingress ethernet port does not power up in the command mode and can only be put into the command mode as a result of a port modeset command being received onto an ingress ethernet port operating in the command mode. A first ingress ethernet port powers up in the command mode. In the command mode the first ingress ethernet port can receive and carry out a port modeset command. Receiving and carrying out of the port modeset command causes one of the ingress ethernet ports identified by the port modeset command to operate in the command mode. A flow table structure adapted to store flow entries is used to determine which egress ethernet port outputs a packet.

Abstract translation: 集成电路包括入口以太网端口和出口以太网端口。 第二个入口以太网端口可配置为以选定的命令模式和数据模式之一运行。 入口以太网端口在命令模式下不上电，只能在端口模式命令接收到在命令模式下运行的入口以太网端口上进入命令模式。 第一个入口以太网端口在命令模式下上电。 在命令模式下，第一个入口以太网端口可以接收并执行端口模式命令。 接收和执行port modeset命令会导致port modeset命令标识的入口以太网端口之一在命令模式下运行。 使用适于存储流条目的流表结构来确定哪个出口以太网端口输出分组。

公开(公告)号：US09417656B2

公开(公告)日：2016-08-16

申请号：US14151688

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: H04L12/743 ,  G06F12/00 ,  H04L29/08 ,  G06F1/10 ,  G06F13/00 ,  G06F9/44

CPC classification number: G06F1/10 ,  G06F9/4498 ,  G06F12/00 ,  G06F13/00 ,  H04L45/7457 ,  H04L67/00

Abstract: An NFA (Non-deterministic Finite Automaton) circuit includes a hardware byte characterizer, a first matching circuit (performs a TCAM match function), a second matching circuit (performs a wide match function), a multiplexer that outputs a selected output from either the first or second matching circuits, and a storage device. N data values stored in first storage locations of the storage device are supplied to the first matching circuit as an N-bit mask value and are simultaneously supplied to the second matching circuit as N bits of an N+O-bit mask value. O data values stored in second storage locations of the storage device are supplied to the first matching circuit as the O-bit match value and are simultaneously supplied to the second matching circuit as O bits of the N+O-bit mask value. P data values stored in third storage locations are supplied onto the select inputs of the multiplexer.

Abstract translation: NFA（非确定性有限自动机）电路包括硬件字节表征器，第一匹配电路（执行TCAM匹配功能），第二匹配电路（执行宽匹配功能），多路复用器，其输出来自 第一或第二匹配电路和存储装置。 存储在存储装置的第一存储位置的N个数据值作为N位掩码值被提供给第一匹配电路，并且作为N + O位掩码值的N位被同时提供给第二匹配电路。 存储在存储装置的第二存储位置的O数据值被提供给第一匹配电路作为O比特匹配值，并且被同时提供给第二匹配电路作为N + O位掩码值的O比特。 存储在第三存储位置的P数据值被提供给多路复用器的选择输入。

公开(公告)号：US09413665B2

公开(公告)日：2016-08-09

申请号：US14464697

申请日：2014-08-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F9/26 ,  H04L12/801 ,  G06F12/10 ,  H04L12/935 ,  H04L12/861 ,  G06F13/16

CPC classification number: H04L47/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F13/4234 ,  G06F2212/657 ,  H04L49/3072 ,  H04L49/9078

Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. A device interacting with the packet engine can use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. Alternatively, the device can use a Linear Addressing Mode (LAM) to communicate with the packet engine. A PAM/LAM selection code field in a bus transaction value sent to the packet engine indicates whether PAM or LAM will be used.

Abstract translation: 在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。 管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 与分组引擎交互的设备可以使用PPI（分组部分标识符）寻址模式（PAM）与分组引擎进行通信，并指示分组引擎存储分组部分。 或者，设备可以使用线性寻址模式（LAM）与分组引擎进行通信。 发送到分组引擎的总线事务值中的PAM / LAM选择代码字段指示是否使用PAM或LAM。

公开(公告)号：US09342313B2

公开(公告)日：2016-05-17

申请号：US14037239

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/00 ,  G06F9/38 ,  G06F9/30 ,  H04L12/741

CPC classification number: G06F9/3836 ,  G06F9/3004 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。