公开(公告)号：US4751671A

公开(公告)日：1988-06-14

申请号：US919795

申请日：1986-10-16

Applicant: William R. Babetski ,  Michael T. Gilmore

Inventor： William R. Babetski ,  Michael T. Gilmore

IPC: G06F5/06 ,  G06F7/76 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F7/764 ,  G06F13/4059 ,  G06F5/065 ,  G06F2205/066

Abstract: A size configurable data storage system that comprises a plurality of main storage buffers and a like plurality of input data buffers with the main storage buffers and input data buffers being interconnected by respective data busses. The data storage system is preferably a FIFO (first-in-first-out) system employing random access memories for storage. To accommodate different word width inputs to the input data buffers, there are provided a plurality of inter-bus buffers which individually intercouple between predetermined data busses. There is also provided a controller which includes an inter-bus buffer control circuit for controlling enabling of the inter-bus buffers in predetermined sets to enable at least one thereof when less than the full width of the main storage buffer is being entered. When a full width word is to be stored then all inter-bus buffers are inhibited providing direct data transfer from all input data buffers to the main storage buffers. The system controller also includes a main storage buffer select circuit for selectively enabling a pattern of main storage buffers under control of an input size control signal. Also included are output data latches which are brought into operation for the reading of data from the RAM storage buffers. Stored data is read out of the main storage buffers in full word widths and the data is then read out of the output data latches in individual word widths. Logic is also included for sensing when the FIFO is full or empty.

Abstract translation: 大小可配置数据存储系统，其包括多个主存储缓冲器和类似的多个输入数据缓冲器，主存储缓冲器和输入数据缓冲器通过相应的数据总线互连。 数据存储系统优选地是采用用于存储的随机存取存储器的FIFO（先进先出）系统。 为了适应输入数据缓冲器的不同的字宽输入，提供了多个串行总线间缓冲器，它们在预定数据总线之间单独地互相耦合。 还提供了一种控制器，其包括一个总线间缓冲器控制电路，用于当小于主存储缓冲器的全部宽度进入时，控制预定组中的总线间缓冲器的使能以使其中的至少一个能够使能。 当要存储全宽字时，禁止所有的总线间缓冲器提供从所有输入数据缓冲区到主存储缓冲器的直接数据传输。 系统控制器还包括主存储缓冲器选择电路，用于在输入尺寸控制信号的控制下选择性地启用主存储缓冲器的模式。 还包括用于从RAM存储缓冲器读取数据的操作的输出数据锁存器。 存储的数据以全字宽度从主存储缓冲器中读出，然后以单个字宽读出输出数据锁存器的数据。 还包括逻辑，用于在FIFO满或空时进行感测。

公开(公告)号：US4689767A

公开(公告)日：1987-08-25

申请号：US790631

申请日：1985-10-22

Applicant: Alexander J. Stevenson ,  David M. Lounsbury

Inventor： Alexander J. Stevenson ,  David M. Lounsbury

IPC: G06F3/06 ,  G06F7/24 ,  G06F13/38

CPC classification number: G06F3/0601 ,  G06F2003/0698

Abstract: A controller for use with a magnetic tape drive which has a plurality of buffer memories for temporarily storing data that is passed between the tape drive and a host computer system. Temporary storage of data within the tape controller allows data to be rewritten on the tape if the initial writing is faulty and allows data read from the tape to be reconstructed if the data has been erroneously recorded.Transfer of information into and out of the buffer circuits is controlled by two independent direct memory access circuits--one circuit transfers data between the host computer system and the buffer memories and the other circuit transfer data between the buffer memories and the tape drive. Each of the direct memory access circuits operates independently of the other, however, both circuits are coordinated by a central processing unit which communicates with the direct memory access units by means of an interrupt arrangement.The controller also contains a serial input/output unit which allows the controller to format and decode a data format that allows synchronous decoding of the data which in turn permits "on the fly" error correction.

Abstract translation: 一种与磁带驱动器一起使用的控制器，其具有用于临时存储在磁带驱动器和主计算机系统之间通过的数据的多个缓冲存储器。 如果初始写入有故障，磁带控制器中的数据临时存储器允许在磁带上重写数据，如果数据被错误地记录，则允许从磁带读取数据。 信息传入和传出缓冲电路由两个独立的直接存储器访问电路控制 - 一个电路在主计算机系统和缓冲存储器之间传送数据，另一个电路在缓冲存储器和磁带驱动器之间传送数据。 每个直接存储器访问电路独立于另一个操作，但是两个电路由通过中断布置与直接存储器访问单元进行通信的中央处理单元进行协调。 该控制器还包含一个串行输入/输出单元，它允许控制器对数据格式进行格式化和解码，数据格式允许数据的同步解码，从而允许“即时”纠错。

公开(公告)号：US4652065A

公开(公告)日：1987-03-24

申请号：US701575

申请日：1985-02-14

Applicant: Edgar R. Cassinelli

Inventor： Edgar R. Cassinelli

IPC: H01R12/04 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K7/10 ,  H01R9/09

CPC classification number: H05K1/141 ,  H05K7/1084 ,  H05K1/023 ,  H05K2201/049 ,  H05K2201/10022 ,  H05K2201/10325 ,  H05K2201/10704 ,  H05K3/3447 ,  H05K3/368 ,  Y10T29/49126

Abstract: A semiconductor termination socket for use with a printed wiring board has a mounting socket base for attachment to the board and plural pin socket receiving elements in the base for connecting to leads of a semiconductor chip package which will be removably inserted into the socket. The socket further has electrical components fabricated within the socket base for connecting a pin of the socket and a termination potential. The electrical components are preferably fabricated using planar technology so that the socket becomes, in essence, a printed wiring board. The semiconductor packages can be of any configuration including, for example, 149 pin grid array packages. If more than one layer of component circuitry is needed, a plurality of layers can be embedded within the mounting socket.

Abstract translation: 与印刷电路板一起使用的半导体终端插座具有用于连接到基板的安装插座底座和底座中的多个插座接收元件，用于连接到可拆卸地插入插座中的半导体芯片封装的引线。 插座还具有在插座底座内制造的电气部件，用于连接插座的插脚和终端电位。 电气部件优选使用平面技术制造，使得插座本质上是印刷电路板。 半导体封装可以是包括例如149针栅格阵列封装的任何配置。 如果需要多于一层的部件电路，则可以在安装插座内嵌入多个层。

公开(公告)号：US4642616A

公开(公告)日：1987-02-10

申请号：US701574

申请日：1985-02-14

Applicant: Peter A. Goodwin

Inventor： Peter A. Goodwin

IPC: H02H3/08 ,  G01R19/145 ,  G01R31/00 ,  G08B21/00

CPC classification number: G01R19/145

Abstract: An apparatus and method for detecting an AC power failure condition employs a fast attack, slow decay, energy storage circuit for tracking an AC input signal and for providing a slowly decaying output based upon a last received peak voltage input value. A current detection circuit monitors the current flow to the storage circuit from the AC mains and generates a current detection signal in response thereto. A power failure condition is declared when either the voltage across the energy storage circuit decays below a selected threshold value or current is not detected flowing to the energy storage circuit at a selected time. A particular current detection circuit employs a high permeability core which is saturated by a current in the sensed line having a current value below an expected peak current flowing to the energy storage circuit. An interrogation pulse periodically energizes an interrogation winding which, in the absence of current in the sensed line, induces a signal across an output winding. When the current being sensed is sufficient to saturate the core, no output signal is generated across the output winding. Circuitry monitors the voltage across the output winding and generates a conditioning signal when even a selected minimum current is not detected in the line at the time of the interrogation pulse.

Abstract translation: 用于检测交流电源故障状况的装置和方法采用快速攻击，慢衰减，用于跟踪AC输入信号的能量存储电路，以及基于最后接收的峰值电压输入值提供缓慢衰减的输出。 电流检测电路监视从AC电源到存储电路的电流流动，并响应于此产生电流检测信号。 当能量存储电路两端的电压衰减低于所选择的阈值或在选定的时间没有检测到流向能量存储电路的电流时，声明电源故障条件。 特定的电流检测电路采用高电导率磁芯，其被感测线路中的电流饱和，电流值低于流向能量存储电路的预期峰值电流。 询问脉冲周期性地激励询问线圈，其在感测线路中没有电流的情况下在输出绕组上感应信号。 当检测到的电流足以使磁芯饱和时，在输出绕组两端不产生输出信号。 电路监视输出绕组两端的电压，并且即使在询问脉冲时线路中未检测到选定的最小电流也会产生调节信号。

公开(公告)号：US4637023A

公开(公告)日：1987-01-13

申请号：US466333

申请日：1983-02-14

Applicant: David M. Lounsbury ,  Alexander J. Stevenson

Inventor： David M. Lounsbury ,  Alexander J. Stevenson

IPC: G11B20/18 ,  G06F11/10

CPC classification number: G11B20/1883 ,  G11B20/1879 ,  G11B2020/183 ,  G11B2220/90

Abstract: Controller circuitry for a serially-recording magnetic tape drive which is capable of correcting writing errors by rewriting the portions of the data which have been erroneously recorded. Write circuitry in the controller breaks a conventional data record up into one or more blockettes, each of which is assigned a unique sequential blockette number which is recorded on the tape along with the data. After each blockette has been serially recorded sequentially by blockette number on the tape, it is immediately read to check whether it has been properly recorded on the tape. If the blockette has been recorded improperly, the read process directs the write circuitry to rerecord the blockette information at the tape position then under the write head. The recorded blockettes may be out of sequential order since the rerecorded blockette may be located several blockettes after its initial erroneous writing. The data is placed back in sequential order by the read process. As blockettes are read from the tape, they are placed in a buffer memory in the controller. The read circuitry then transfers the data to the host computer system in the order specified by the blockette number and therefore reconstructs the data even if blockettes have been rewritten out of sequence.

Abstract translation: 用于串行记录磁带驱动器的控制器电路，其能够通过重写已经被错误记录的数据的部分来校正写入错误。 控制器中的写入电路会将传统的数据记录中断到一个或多个单元中，每个单元都被分配一个唯一的顺序单元编号，它与数据一起记录在磁带上。 在通过磁带上的封锁号顺序地顺序地记录每个封锁片之后，立即读取以检查其是否已经被正确记录在磁带上。 如果封堵器被不正确地记录，则读取过程指示写入电路在磁带位置上再写入写入信息，然后在写入头下面。 记录的封锁可能不顺序，因为在其初始错误写入之后，重新记录的封锁可能位于几个封锁块。 通过读取过程按顺序将数据放回。 当从磁带读取封锁片时，它们被放置在控制器中的缓冲存储器中。 然后，读取电路按照封锁号码指定的顺序将数据传送到主机系统，因此即使封锁块已被重新排列，也重建数据。

公开(公告)号：US4601586A

公开(公告)日：1986-07-22

申请号：US579090

申请日：1984-02-10

Applicant: Richard G. Bahr ,  Daryl F. Kinney ,  Alan G. Nemeth ,  Helen S. Raizen

Inventor： Richard G. Bahr ,  Daryl F. Kinney ,  Alan G. Nemeth ,  Helen S. Raizen

IPC: G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  H04J3/26

CPC classification number: G06F15/161 ,  G06F13/385 ,  G06F15/17

Abstract: A system for transferring solicited message packets between data processors coupled on a serial communications path. A solicitor processor allocates a portion of its memory for storage of solicited message packets which might be solicited and received from at least one other data processor. The solicitor data processor defines a sequence of operations to be performed on any such received solicited message packets at that processor. The solicitor processor also transfers a solicited message parameter signal to the solicitee data processor where that signal is representative of a predetermined header portion for solicited data packets which might be generated by the solicitee data processor and transferred to the solicitor data processor. The header portion of a solicited message packet relates one or more of the sequences of operations which are to be associated with that packet. At least one of the other data processors receives any solicited message parameter signal addressed to that solicitee data processor. The solicitee processor is responsive to a received message parameter signal to generate a solicited message packet (with a header portion, as defined by the solicited message parameter signal) for transfer to the solicitor processor. The solicitor processor receives any such transmitted solicited message packet and stores that packet in the allocated portion of memory.

Abstract translation: 一种用于在耦合在串行通信路径上的数据处理器之间传送请求的消息分组的系统。 律师处理器分配其存储器的一部分用于存储可能从至少一个其他数据处理器请求和接收的所请求的消息分组。 律师数据处理器定义将在该处理器处对任何这样接收到的请求消息分组执行的操作序列。 律师处理器还将请求的消息参数信号传送到请求者数据处理器，其中该信号代表可能由请求者数据处理器生成并传送给律师数据处理器的请求数据分组的预定报头部分。 所请求的消息分组的报头部分涉及要与该分组相关联的操作序列中的一个或多个。 至少其中一个数据处理器接收寻址到该请求数据处理器的任何请求消息参数信号。 索引处理器响应于接收到的消息参数信号以产生被请求的消息分组（具有由所请求的消息参数信号定义的报头部分）以便传送到律师处理器。 律师处理器接收任何此类发送的请求消息分组，并将该分组存储在所分配的存储器部分中。

公开(公告)号：USD282469S

公开(公告)日：1986-02-04

申请号：US512681

申请日：1983-07-11

Applicant: Joseph A. Lemoine, Jr. ,  Daniel A. Ferrara, Jr. ,  David Robillard

Designer： Joseph A. Lemoine, Jr. ,  Daniel A. Ferrara, Jr. ,  David Robillard

公开(公告)号：US4566000A

公开(公告)日：1986-01-21

申请号：US466077

申请日：1983-02-14

Applicant: Craig E. Goldman ,  Douglas A. Voorhies

Inventor： Craig E. Goldman ,  Douglas A. Voorhies

IPC: G09G5/08 ,  G09G1/00

CPC classification number: G09G5/08

Abstract: Image display equipment has a memory element for storing a selected combinatorial function of a cursor pattern and image field existing at an addressed cursor position, and has a controllable selector for displaying, at the cursor field, either the image field or the combined cursor field and image pattern. A single display memory can store the image field, the cursor pattern, and the selected combination of cursor pattern and image field. Selection logic addresses the stored combination pattern in lieu of the image field to provide the desired cursor display at the addressed cursor position.

Abstract translation: 图像显示设备具有用于存储存在于寻址光标位置的光标图案和图像场的选定组合功能的存储元件，并且具有可控选择器，用于在光标位置显示图像场或组合光标域，以及 图像模式。 单个显示存储器可以存储图像字段，光标图案以及所选择的光标图案和图像字段的组合。 选择逻辑寻址存储的组合模式以代替图像字段，以在寻址的光标位置提供期望的光标显示。

公开(公告)号：USD281607S

公开(公告)日：1985-12-03

申请号：US465321

申请日：1983-02-09

Applicant: Jerry C. Marino ,  David E. Desilets

Designer： Jerry C. Marino ,  David E. Desilets

公开(公告)号：USD280509S

公开(公告)日：1985-09-10

申请号：US465323

申请日：1983-02-09

Applicant: Jerry C. Marino ,  Steven W. Collins

Designer： Jerry C. Marino ,  Steven W. Collins