公开(公告)号：US20110082965A1

公开(公告)日：2011-04-07

申请号：US12572189

申请日：2009-10-01

Applicant: Pranay Koka ,  Michael Oliver McCracken ,  Herbert Dewitt Schwetman, JR. ,  Jan Lodewijk Bonebakker

Inventor： Pranay Koka ,  Michael Oliver McCracken ,  Herbert Dewitt Schwetman, JR. ,  Jan Lodewijk Bonebakker

IPC: G06F12/00 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0866 ,  G06F12/10 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/214

Abstract: A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Abstract translation: 系统包括使用处理器总线网络耦合的多个节点。 多个节点包括第一处理器节点，包括一个或多个处理核心和主存储器，以及经由处理器总线网络的第一处理器总线耦合到第一处理器节点的闪存节点。 闪速存储器节点包括闪速存储器，其包括闪存页，第一存储器，其包括用于存储闪速存储器中的闪存页的高速缓存闪存页的高速缓存分区;以及用于存储高速缓存控制数据的控制分区和访问闪存页的请求的上下文 以及包括直接存储器访问（DMA）寄存器并被配置为经由第一处理器总线从第一处理器节点接收第一请求以访问闪存页的逻辑模块。

公开(公告)号：US20110078110A1

公开(公告)日：2011-03-31

申请号：US12569496

申请日：2009-09-29

Applicant: Manoj Paul Joseph

Inventor： Manoj Paul Joseph

IPC: G06F17/30 ,  G06F12/00 ,  G06F12/16 ,  G06F7/00

CPC classification number: G06F17/30174 ,  G06F17/30368 ,  G06F17/30581 ,  G06F17/30607

Abstract: In general, the invention relates to replicating a source file system stored on a first memory by obtaining a first unread entry from a changelog associated with the source file system, querying the source file system using the first unread entry to obtain a current first object file status, a current first object file path, a current first parent directory status, and a current first parent directory path, determining, based on the querying, whether a first object file on the source file system has changed at some time after the execution of the first unread entry, if the first object file has not changed, performing a first action on a target file system, and if the first object file has changed, performing a second action on the target file system.

Abstract translation: 通常，本发明涉及通过从与源文件系统相关联的变更日志获取第一未读条目来复制存储在第一存储器上的源文件系统，使用第一未读条目查询源文件系统以获得当前第一目标文件 状态，当前第一目标文件路径，当前第一父目录状态和当前第一父目录路径，基于查询确定源文件系统上的第一目标文件是否在执行 所述第一未读条目，如果所述第一对象文件没有改变，则在目标文件系统上执行第一动作，并且如果所述第一对象文件已经改变，则对所述目标文件系统执行第二动作。

公开(公告)号：US20110075380A1

公开(公告)日：2011-03-31

申请号：US12568017

申请日：2009-09-28

Applicant: Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

Inventor： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

IPC: H05K1/14 ,  H05K3/36

CPC classification number: H05K3/303 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/09036 ,  H05K2201/1059 ,  H05K2201/209 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.

Abstract translation: 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征可重新机械耦合。 这些积极和消极的特征可以彼此交配和自锁。 例如，其中一个表面上的阳性特征可以包括成对的相对的微弹簧，并且负特征可以包括在另一个表面上的凹坑或凹槽。 当基板机械耦合时，给定的一对正特征可以在另一表面的平面中提供力。 此外，通过压缩MCM使得基板的表面彼此推动，可以释放机械联接。

公开(公告)号：US20110069973A1

公开(公告)日：2011-03-24

申请号：US12564701

申请日：2009-09-22

Applicant: Ashok V. Krishnamoorthy ,  Xuezhe Zheng

Inventor： Ashok V. Krishnamoorthy ,  Xuezhe Zheng

IPC: H04B10/12

CPC classification number: G02B6/423 ,  G02B6/12 ,  G02B6/30 ,  G02B6/36 ,  G02B6/42 ,  G02B6/4228 ,  G02B6/4231 ,  G02B6/43 ,  H04B10/803

Abstract: An optical module is described. This optical module includes at least two optical devices that communicate with each other using edge-to-edge optical coupling of an optical signal between optical components in the two optical devices. Note that the edge-to-edge optical coupling may occur without mode converters at edges of either of the optical devices. Furthermore, the edge-to-edge optical coupling may be facilitated by an alignment substrate, which is mechanically coupled to the two optical devices. This alignment substrate aligns the edges of the two optical devices so that they are approximately parallel to each other, and aligns the optical components in the two optical devices.

Abstract translation: 描述光学模块。 该光学模块包括使用两个光学装置中的光学部件之间的光信号的边缘到边缘光耦合来彼此通信的至少两个光学装置。 注意，边缘到边缘光耦合可能在任何光学器件的边缘处没有模式转换器。 此外，边缘到边缘光耦合可以通过机械耦合到两个光学器件的对准衬底来促进。 该对准衬底对准两个光学器件的边缘，使得它们彼此近似平行，并对准两个光学器件中的光学部件。

公开(公告)号：US20110068827A1

公开(公告)日：2011-03-24

申请号：US12566506

申请日：2009-09-24

Applicant: Tamer M. Ali ,  Robert J. Drost ,  Chih-Kong Ken Yang

Inventor： Tamer M. Ali ,  Robert J. Drost ,  Chih-Kong Ken Yang

IPC: H03D13/00

CPC classification number: H03D13/00

Abstract: A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal.

Abstract translation: 描述了相位插值器电路。 在相位插值器电路中，基于第一参考信号和第二参考信号的加权求和产生具有基频和相位的输出信号，其中第一参考信号具有基频和第一相位 ，第二参考信号具有相同的基频和第二相位。 注意，基于相位插值器电路中的加权电路中的相关联的第一和第二阻抗值来确定第一参考信号和第二参考信号对输出信号的贡献。 例如，可以使用两个电容器的可编程电容比来在第一参考信号和第二参考信号之间进行内插。 另外，相位插值器电路可以包括向加权电路提供DC偏置并且放大加权电路的输出以提供输出信号的偏置电路。

公开(公告)号：US20110067107A1

公开(公告)日：2011-03-17

申请号：US12625031

申请日：2009-11-24

Applicant: John E. Weeks ,  Christoph L. Schuba

Inventor： John E. Weeks ,  Christoph L. Schuba

IPC: H04L9/32 ,  G06F12/14

CPC classification number: H04L63/1416 ,  G06F21/55 ,  G06F2221/2105 ,  H04L63/0209 ,  H04L63/1491

Abstract: Methods and apparatus are provided for integrated deflection, detection and intrusion. Within a single computer system configured for operating system virtualization (e.g., Solaris, OpenSolaris), multiple security functions execute in logically independent zones or containers, under the control and administration of a global zone. Such functions may illustratively include a demilitarized zone (DMZ) and a honeypot. Management is facilitated because all functions work within a single operating system, which promotes the ability to configure, monitor and control each function. Any given zone can be configured with limited resources, a virtual network interface circuit and/or other features.

Abstract translation: 提供了集成的偏转，检测和入侵的方法和装置。 在配置为操作系统虚拟化的单个计算机系统（例如，Solaris，OpenSolaris）中，在全局区域的控制和管理下，在逻辑上独立的区域或容器中执行多个安全功能。 这种功能可以说明性地包括非军事区（DMZ）和蜜罐。 因为所有功能都可以在单个操作系统中运行，从而促进了配置，监视和控制各项功能的能力，从而促进了管理。 任何给定的区域都可以配置有限的资源，虚拟网络接口电路和/或其他功能。

公开(公告)号：US20110051357A1

公开(公告)日：2011-03-03

申请号：US12549542

申请日：2009-08-28

Applicant: DEREK ORR ,  STUART J. MCGURNAGHAN

Inventor： DEREK ORR ,  STUART J. MCGURNAGHAN

IPC: G06F1/20

CPC classification number: G06F1/20

Abstract: A system and method of spread-spectrum fan control for an air-cooled system is provided for reducing the vibrational and acoustical noise associated with the air-cooled system. The method includes generating a first control signal that controls a blade-passing frequency of a first cooling fan and a second control signal that controls a blade-passing frequency of a second cooling fan, wherein the first and second control signals may be pulse width modulated (“PWM”) signals. One or more noise generators independently vary duty cycles for the first and second PWM signals within a range around respective first and second blade-passing frequency set points. As a result, the blade-passing frequencies for the first and second cooling fans are independently and randomly modulated within a range around the respective first and second blade-passing frequency set points.

Abstract translation: 提供了一种用于风冷系统的扩频风扇控制的系统和方法，用于降低与风冷系统相关联的振动和声音噪声。 该方法包括产生控制第一冷却风扇的叶片通过频率的第一控制信号和控制第二冷却风扇的叶片通过频率的第二控制信号，其中第一和第二控制信号可以是脉宽调制 （“PWM”）信号。 一个或多个噪声发生器在相应的第一和第二叶片通过频率设定点的范围内独立地改变第一和第二PWM信号的占空比。 结果，第一和第二冷却风扇的叶片通过频率在相应的第一和第二叶片通过频率设定点周围的范围内独立随机调制。

公开(公告)号：US20110035561A1

公开(公告)日：2011-02-10

申请号：US12538717

申请日：2009-08-10

Applicant: Haakan E. Zeffer ,  Robert E. Cypher ,  Shailender Chaudhry

Inventor： Haakan E. Zeffer ,  Robert E. Cypher ,  Shailender Chaudhry

IPC: G06F12/02

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/522

Abstract: Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.

Abstract translation: 本发明的一些实施例提供了一种用于操作存储队列的系统，其中存储队列缓冲正在等待被提交到处理器中的存储器系统的存储。 在操作期间，系统检查商店队列头部的条目。 如果条目包含一个签名，系统将检查一个未确认的计数器，该计数器可以跟踪从存储队列发送到内存系统但尚未被确认为提交到内存系统的存储操作数。 如果未确认的计数器不为零，则系统将等待直到未确认的计数器等于零，然后从存储队列中删除该元素令牌。

公开(公告)号：US07886300B1

公开(公告)日：2011-02-08

申请号：US11528188

申请日：2006-09-26

Applicant: Dean R. E. Long ,  Yin Zin Mark Lam ,  Jiangli Zhou

Inventor： Dean R. E. Long ,  Yin Zin Mark Lam ,  Jiangli Zhou

IPC: G06F9/46 ,  G06F12/00 ,  G06F13/28

CPC classification number: G06F9/526 ,  G06F9/5016

Abstract: A mechanism is disclosed for implementing fast locking in a multi-threaded system. This mechanism enables fast locking to be performed even on an operating system platform that does not allow one thread to assign ownership of a lock on a mutex to another thread. In addition, the mechanism performs locking in a manner that ensures priority correctness and is low-memory safe. In one implementation, the priority correctness is achieved by using operating system mutexes to implement locking, and the low-memory safe aspect is achieved by pre-allocating a memory section to each thread. This pre-allocated memory section ensures that a thread will have sufficient memory to obtain a lock, even when a system is in a low-memory state. With this mechanism, it is possible to implement locking in a safe and efficient manner.

Abstract translation: 公开了一种用于在多线程系统中实现快速锁定的机构。 这种机制使得即使在不允许一个线程将互斥体上的锁的所有权分配给另一个线程的操作系统平台上也能够执行快速锁定。 此外，该机制以确保优先级正确性并且具有低内存安全性的方式执行锁定。 在一个实现中，通过使用操作系统互斥体实现锁定来实现优先级正确性，并且通过向每个线程预先分配存储器部分来实现低内存安全方面。 这个预分配的存储器部分确保线程将具有足够的存储器以获得锁定，即使系统处于低内存状态。 利用这种机制，可以以安全有效的方式实现锁定。

公开(公告)号：US20110010696A1

公开(公告)日：2011-01-13

申请号：US12500282

申请日：2009-07-09

Applicant: Sheldon M. Lobo ,  Fu-Hwa Wang

Inventor： Sheldon M. Lobo ,  Fu-Hwa Wang

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/4435 ,  G06F8/4434 ,  G06F9/449

Abstract: One or more embodiments of the present invention relate to a method for duplicate virtual function table removal. The method includes identifying, using a processor of a computer, a first virtual function table formed when a first source code is compiled into a first object code. The method further includes using the processor, identifying a second virtual function table formed when a second source code is compiled into a second object code. The method further includes, independent of linking the first object code to a first executable binary code and the second object code to a second executable binary code, identifying, using the processor, that the first virtual function table and the second virtual function table are identical and, using the processor, deleting the second virtual function table.

Abstract translation: 本发明的一个或多个实施例涉及一种用于重复虚拟功能表移除的方法。 该方法包括使用计算机的处理器识别当第一源代码被编译成第一目标代码时形成的第一虚拟功能表。 该方法还包括使用处理器，识别当第二源代码被编译成第二目标代码时形成的第二虚拟功能表。 该方法还包括：独立于将第一目标代码与第一可执行二进制代码链接，将第二目标代码链接到第二可执行二进制代码，使用处理器识别第一虚拟函数表和第二虚拟函数表相同 并且使用所述处理器，删除所述第二虚拟功能表。