公开(公告)号：US20160259757A1

公开(公告)日：2016-09-08

申请号：US15033459

申请日：2014-10-28

Applicant: SILICON TAILOR LIMITED

Inventor： Paul Metzgen

IPC: G06F15/78 ,  G06F1/10

CPC classification number: G06F15/7867 ,  G06F1/10 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/3873 ,  G06F9/3897 ,  G06F15/7878

Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

Abstract translation: 一种能够同时处理多个线程的可配置处理电路，该电路包括线程数据存储器，多个可配置执行单元，用于将线程数据存储器中的位置连接到执行单元的可配置路由网络，用于存储配置的配置数据存储 每个定义路由网络的配置和多个执行单元中的一个或多个的配置的实例，以及由执行单元，路由网络和线程数据存储器形成的流水线，该流水线包括多个管道部分，其被配置为 每个线程在每个时钟周期从一个流水线段传播到下一个线程，该电路被配置为：（i）将每个线程与配置实例相关联; 并且（ii）将每个时钟周期的多个流水线段中的每一个配置为与时钟周期内将通过该流水线部分传播的相应线程相关联的配置实例。

公开(公告)号：US09244883B2

公开(公告)日：2016-01-26

申请号：US12716027

申请日：2010-03-02

Applicant: Jae-un Park ,  Ki-seok Kwon ,  Sang-suk Lee

Inventor： Jae-un Park ,  Ki-seok Kwon ,  Sang-suk Lee

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/7867 ,  G06F9/30189 ,  G06F9/3897

Abstract: A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration data in advance into the configuration memory when booting commences. Accordingly, a reduction in capacity of a configuration memory may be achieved.

Abstract translation: 提供了一种用于控制可重构处理器的技术。 代替在启动开始时将所有编译的配置数据预先加载到配置存储器中，可重配置处理器在执行程序时将配置数据从外设存储器动态地加载到配置存储器。 因此，可以实现配置存储器的容量的降低。

公开(公告)号：US09170812B2

公开(公告)日：2015-10-27

申请号：US14572643

申请日：2014-12-16

Applicant: PACT XPP TECHNOLOGIES AG

Inventor： Martin Vorbach ,  Jürgen Becker ,  Markus Weinhardt ,  Volker Baumgarte ,  Frank May

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/08 ,  G06F15/78 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F15/80 ,  G06F9/3001 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/3455 ,  G06F9/3877 ,  G06F9/3897 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F15/7814 ,  G06F15/7867 ,  G06F2212/452

Abstract: A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

Abstract translation: 具有数据处理核心和集成流水线阵列数据处理器的数据处理系统和用于存储由流水线阵列数据处理器处理的算法列表的缓冲器。

公开(公告)号：US09146896B2

公开(公告)日：2015-09-29

申请号：US12795462

申请日：2010-06-07

Applicant: Hiroshi Furukawa ,  Ichiro Kasama

Inventor： Hiroshi Furukawa ,  Ichiro Kasama

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30145 ,  G06F9/34 ,  G06F9/3879 ,  G06F9/3897 ,  G06F12/02 ,  G06F15/7867 ,  G06F2212/1021

Abstract: A computer system that includes a central processing unit, a random-access-memory interface, a random-access memory whose addresses are allocated in an address space of the random-access-memory interface, and a reconfigurable arithmetic device is described herein. The reconfigurable arithmetic device includes input terminals, output terminals, a network of plurality of processor elements, a built-in random-access memory, a control unit, an inter-processor-element network and a configuration-data memory. In accordance with configuration on data from the configuration-data memory, the inter processor-element network is capable of changing the connection state of the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, and the arithmetic function of the reconfigurable arithmetic device is capable of being dynamically changed.

Abstract translation: 本文描述了一种包括中央处理单元，随机存取存储器接口，其地址分配在随机存取存储器接口的地址空间中的随机存取存储器的计算机系统，以及可重构运算装置。 可重构算术装置包括输入端子，输出端子，多个处理器元件的网络，内置随机存取存储器，控制单元，处理器间元件网络和配置数据存储器。 根据来自配置数据存储器的数据配置，处理器间网络能够将输入端子和输出端子的连接状态改变为多个处理器元件的输入端口和输出端口，并且算术 能够动态地改变可重构运算装置的功能。

公开(公告)号：US20150227375A1

公开(公告)日：2015-08-13

申请号：US14024495

申请日：2013-09-11

Applicant: ROBERT KEITH MYKLAND

Inventor： ROBERT KEITH MYKLAND

IPC: G06F9/38 ,  G06F15/78

CPC classification number: G06F15/7867 ,  G06F8/41 ,  G06F9/3869 ,  G06F9/3873 ,  G06F9/3897

Abstract: A method and system for enabling persistence of a value by a dynamically reconfigurable processor (“DRP”) from the time of execution of an earlier executed instruction to a time of later executed instruction. The value may represent a constant a variable value of a software program. The value may be read from or written into a memory circuit, a DRP logic element, an iterator of a DRP logic element, or other value storing element or aspect of the DRP. The value may be maintained in a single logic element through the duration of one or more instruction execution cycles, or alternatively or additionally, the value may be transferred between or among one or more value storage hardware elements. The persistence of the value and transfer of the value within, into and/or out of the DRP enables later access of the value by, and/or positioning the value within, the DRP.

Abstract translation: 一种方法和系统，用于从执行先前执行的指令时到稍后执行的指令的时间，通过动态可重配置处理器（“DRP”）使得持久化值。 该值可以表示软件程序的变量值的常数。 该值可以从存储器电路，DRP逻辑元件，DRP逻辑元件的迭代器或存储DRP的元件或方面的其他值读取或写入。 该值可以在一个或多个指令执行周期的持续时间内保持在单个逻辑元件中，或者或者另外地，该值可以在一个或多个值存储硬件元件之间或之间传送。 价值的持续存在以及DRP内部和/或之外的价值的传递使得能够在DRP中随后访问该价值和/或定位该价值。

公开(公告)号：US09063735B2

公开(公告)日：2015-06-23

申请号：US13272846

申请日：2011-10-13

Applicant: Hee-Jin Ahn ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

Inventor： Hee-Jin Ahn ,  Dong-Hoon Yoo ,  Bernhard Egger ,  Min-Wook Ahn ,  Jin-Seok Lee ,  Tai-Song Jin ,  Won-Sub Kim

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/325 ,  G06F9/3838 ,  G06F9/3897

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract translation: 提供了一种可重构处理器，其能够通过分析存储器访问指令之间的依赖性并且基于分析结果在多个处理元件（PE）之间分配存储器访问指令，从而降低错误计算的概率，以及 控制可重构处理器的方法。 可重配置处理器从模拟结果中提取执行跟踪，并且基于存储器访问指令的执行跟踪的部分来分析包括在不同迭代中的指令之间的存储器依赖性。

公开(公告)号：US20150143086A1

公开(公告)日：2015-05-21

申请号：US14082088

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8076

Abstract: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

Abstract translation: 公开了在向量数据存储器和执行单元之间的数据流路径中采用格式转换电路的矢量处理引擎（VPE），以向输入矢量数据提供转换为执行单元的向量处理操作。 还公开了相关矢量处理器系统和方法。 在VPE中的矢量数据存储器和执行单元之间的数据流路径中提供格式转换电路。 格式转换电路被配置为将输入矢量数据样本集合在数据流路径上提供给要处理的执行单元的同时，将从输入向量数据存储器中取出的输入向量数据样本集合进行转换。 以这种方式，输入向量数据样本集的格式转换不需要从向量数据存储器进行预处理，存储和重新获取，从而通过格式转换预处理来降低功耗并且不限制数据流路径的效率 延误

公开(公告)号：US20150106596A1

公开(公告)日：2015-04-16

申请号：US14572643

申请日：2014-12-16

Applicant: PACT XPP TECHNOLOGIES AG

Inventor： Martin Vorbach ,  Jürgen Becker ,  Markus Weinhardt ,  Volker Baumgarte ,  Frank May

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F15/80 ,  G06F9/3001 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/3455 ,  G06F9/3877 ,  G06F9/3897 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F15/7814 ,  G06F15/7867 ,  G06F2212/452

Abstract: A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

Abstract translation: 具有数据处理核心和集成流水线阵列数据处理器的数据处理系统和用于存储由流水线阵列数据处理器处理的算法列表的缓冲器。

公开(公告)号：US20140208087A1

公开(公告)日：2014-07-24

申请号：US14222194

申请日：2014-03-21

Applicant: SYNOPSYS, INC.

Inventor： James Robert-Howard Hakewill ,  Richard A. Fuhler

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F5/01 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/32 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3885 ,  G06F9/3897 ,  G06F11/3648 ,  G06F12/0802 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor.

Abstract translation: 具有可扩展逻辑的微处理器架构。 一个或多个定制应用程序可用于指令流水线。 可定制的应用可以包括软件，扩展逻辑指令或寄存器，动态可配置的硬件逻辑或这些的组合。 为了使操作系统能够与定制的扩展应用程序接口，至少提供一个软件扩展到操作系统。 当请求特定扩展时，操作系统会生成软件异常。 响应于异常，调用至少一个软件扩展来处理微处理器的可扩展逻辑的上下文切换和动态配置。

公开(公告)号：US20130151793A1

公开(公告)日：2013-06-13

申请号：US13763695

申请日：2013-02-10

Applicant: Element CXI, LLC

Inventor： John M. Rudosky ,  Steven Hennick Kelem ,  Stephen L. Wasson ,  Brian A. Box

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F9/3897 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17796

Abstract: The exemplary embodiments provide a multi-context configurable memory controller comprising: an input-output data port array comprising a plurality of input queues and a plurality of output queues; at least one configuration and control register to store, for each context of a plurality of contexts, a plurality of configuration bits; a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts, the plurality of data operations comprising memory address generation, memory write operations, and memory read operations, the configurable circuit element comprising a plurality of configurable address generators; and an element controller, the element controller comprising a port arbitration circuit to arbitrate among a plurality of contexts having a ready-to-run status, and the element controller to allow concurrent execution of multiple data operations for multiple contexts having the ready-to-run status.

Abstract translation: 示例性实施例提供了一种多上下文可配置存储器控制器，包括：包括多个输入队列和多个输出队列的输入 - 输出数据端口阵列; 至少一个配置和控制寄存器，用于为多个上下文的每个上下文存储多个配置位; 可配置用于多个数据操作的可配置电路元件，每个数据操作对应于多个上下文的上下文，所述多个数据操作包括存储器地址生成，存储器写入操作和存储器读取操作，所述可配置电路元件包括： 多个可配置的地址发生器; 以及元件控制器，所述元件控制器包括端口仲裁电路，以在具有准备运行状态的多个上下文之间进行仲裁，并且所述元件控制器允许并行执行多个上下文的多个数据操作， 运行状态。