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    ADDRESSING FOR INTEGRATED CIRCUITS
    11.
    发明公开
    ADDRESSING FOR INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20240178841A1

    公开(公告)日：2024-05-30

    申请号：US18507524

    申请日：2023-11-13

    申请人： Nokia Solutions and Networks Oy

    发明人： Mustafa SAYGINER

    IPC分类号： H03K19/0185 ,  H03K19/094

    CPC分类号： H03K19/018585 ,  H03K19/09425

    摘要： Disclosed is a method comprising determining that a signal is to be provided to a beamformer integrated circuit using a control interface associated with the beamformer integrated circuit, identifying, within, at least one memory, a unique address of the beamformer integrated circuit, wherein the beamformer integrated circuit is aware of own unique address based on a set state of an address pin of the beamformer integrated circuit, wherein the set state of the address pin is one of at least three available set states, the set state being provided as an input to three logical buffers electrically coupled to the beamformer integrated circuit, and outputs from the three logical buffers being combined using a logical encoder that generates the unique address, and providing the signal to the beamformer integrated circuit using the unique address.

    OSCILLATOR
    14.
    发明申请
    OSCILLATOR 审中-公开

    公开(公告)号：US20180351508A1

    公开(公告)日：2018-12-06

    申请号：US15808132

    申请日：2017-11-09

    申请人： SK hynix Inc.

    发明人： Min Soon HWANG

    IPC分类号： H03B5/04 ,  H03L7/099 ,  H03L7/091 ,  H03K19/094 ,  H03M1/66

    CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K19/09425 ,  H03L7/0991 ,  H03L7/0995 ,  H03L2207/50 ,  H03M1/745

    摘要： Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.

    Multi-threshold flash NCL logic circuitry with flash reset
    16.
    发明授权
    Multi-threshold flash NCL logic circuitry with flash reset 有权
    多阈值闪存NCL逻辑电路，具有闪存复位功能

    公开(公告)号：US09385715B2

    公开(公告)日：2016-07-05

    申请号：US14703483

    申请日：2015-05-04

    申请人： Wave Semiconductor, Inc.

    发明人： Gajendra Prasad Singh

    IPC分类号： H03K19/00 ,  H03K19/094 ,  H03K19/23 ,  H03K23/40 ,  H03K23/58 ,  H03K19/096

    CPC分类号： H03K19/0013 ,  H03K19/094 ,  H03K19/09425 ,  H03K19/096 ,  H03K19/23 ,  H03K23/40 ,  H03K23/58

    摘要： Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

    摘要翻译： 多阈值闪存Null Convention Logic（NCL）在闪存NCL门内包括一个或多个高阈值电压晶体管，以减少由NCL门晶体管的电流泄漏引起的功耗。 可以添加高阈值电压晶体管和/或可以代替NCL门的一个或多个低电压阈值晶体管。 上拉路径中包含高Vt器件，以在闪存NCL逻辑门处于空状态时降低功耗。

    DATA OUTPUT CIRCUIT
    17.
    发明申请
    DATA OUTPUT CIRCUIT 审中-公开
    数据输出电路

    公开(公告)号：US20110102024A1

    公开(公告)日：2011-05-05

    申请号：US12825780

    申请日：2010-06-29

    申请人： Seong Seop LEE ,  Saeng Hwan KIM

    发明人： Seong Seop LEE ,  Saeng Hwan KIM

    IPC分类号： H03K3/00

    CPC分类号： H03K19/018507 ,  H03K19/09425

    摘要： The data output circuit includes a pull-up signal generator, a pull-down signal generator and a driver. The pull-up signal generator is configured to generate a pull-up signal that is driven to a first level state when a pre-pull-up signal is activated and driven to a second level state after a first delay period. The pull-down signal generator is configured to generate a pull-down signal that is driven to a third level state when a pre-pull-down signal is activated and driven to a fourth level state after a second delay period. The driver is configured to drive output data in response to receiving either the pull-up signal and the pull-down signal.

    摘要翻译： 数据输出电路包括上拉信号发生器，下拉信号发生器和驱动器。 上拉信号发生器被配置为产生上拉信号，当上拉上拉信号被激活并被驱动到第一延迟时段之后的第二电平状态时，该上拉信号被驱动到第一电平状态。 下拉信号发生器被配置为产生下拉信号，当下拉下拉信号被激活并且在第二延迟周期之后被驱动到第四电平状态时，该下拉信号被驱动到第三电平状态。 驱动器被配置为响应于接收到上拉信号和下拉信号而驱动输出数据。

    MULTI-LEVEL SIGNALING
    18.
    发明申请
    MULTI-LEVEL SIGNALING 有权
    多级信号

    公开(公告)号：US20110018517A1

    公开(公告)日：2011-01-27

    申请号：US12858990

    申请日：2010-08-18

    申请人： Anthony B. Candage ,  Gary D. Polhemus ,  Hrvoje Jasa ,  Robert T. Carroll

    发明人： Anthony B. Candage ,  Gary D. Polhemus ,  Hrvoje Jasa ,  Robert T. Carroll

    IPC分类号： G05F1/10

    CPC分类号： H02M3/1584 ,  H02M2001/0012 ,  H03K19/0002 ,  H03K19/09425

    摘要： A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

    摘要翻译： 控制电路通过将输出编码成具有至少三个状态的多状态信号，来产生基于第一信号和第二信号的输出。 由控制器产生的多态信号的大小根据第一信号和第二信号的二进制状态而变化。 控制器利用输出（即多态信号）来控制开关电路。 驱动电路接收由控制电路产生的输出。 在一个实施例中，多状态信号具有多于两个不同的逻辑状态。 驱动器解码用于产生信号的多态信号以控制开关电路中的开关。 由驱动电路产生的一个信号是脉宽调制信号; 由驱动电路产生的另一信号是使能/禁止信号。

    TERNARY VALVE INPUT CIRCUIT
    19.
    发明申请
    TERNARY VALVE INPUT CIRCUIT 有权
    三通阀输入电路

    公开(公告)号：US20090309630A1

    公开(公告)日：2009-12-17

    申请号：US12484670

    申请日：2009-06-15

    申请人： Hideo ITO

    发明人： Hideo ITO

    IPC分类号： H03K19/00

    CPC分类号： H03K19/09425 ,  H03K19/0002

    摘要： A pull-up switching device for controlling connection and non-connection of an input terminal IN and a first supply VDD and a pull-down switching device for controlling connection and non-connection of the input terminal IN and a second supply VSS are provided. The pull-up switching device and the pull-down switching device are operated exclusively on and off in time division to hold and output the state of the input terminal during each operating state from the two output terminals.

    摘要翻译： 提供一种用于控制输入端子IN和第一电源VDD的连接和不连接的上拉开关装置以及用于控制输入端子IN和第二电源VSS的连接和不连接的下拉开关装置。 上拉开关装置和下拉开关装置在时间上专门开和关，以在两个输出端子的每个操作状态期间保持和输出输入端子的状态。

    Method and apparatus for multi-level input voltage receiver circuit
    20.
    发明授权
    Method and apparatus for multi-level input voltage receiver circuit 失效
    多电平输入电压接收电路的方法和装置

    公开(公告)号：US5748028A

    公开(公告)日：1998-05-05

    申请号：US741731

    申请日：1996-10-31

    申请人： Douglas Ele Martin

    发明人： Douglas Ele Martin

    IPC分类号： H03K19/017 ,  H03K19/094 ,  H03K17/04

    CPC分类号： H03K19/09425 ,  H03K19/01721

    摘要： The invention is embodied in a receiver and a method for responding to an input signal. The input signal is received in a first stage of the receiver, which generates a first stage output signal responsive thereto. If the input signal does not exceed a first level, the first stage output signal is generated by an overvoltage element. That is, for this case, the overvoltage element passes the input signal through to the first stage output, and the first stage output voltage is not increased by a first stage pullup element. If, on the other hand, the input signal exceeds the first level, the first stage output signal voltage level is increased by the first stage pullup element to a higher output voltage level. The output signal from the first stage is received in a second stage. The second stage generates a second stage output responsive thereto. A second stage pullup element may be disabled by a mode signal in expectation that the input signal will exceed the first level, so that the first stage output voltage will not be increased by the second stage pullup element.

    摘要翻译： 本发明体现在接收机和用于响应输入信号的方法中。 输入信号在接收机的第一级接收，其响应于此产生第一级输出信号。 如果输入信号不超过第一电平，则第一级输出信号由过电压元件产生。 也就是说，在这种情况下，过电压元件将输入信号传递到第一级输出，并且第一级上拉元件不会增加第一级输出电压。 另一方面，如果输入信号超过第一电平，则第一级上拉元件将第一级输出信号电压电平增加到更高的输出电压电平。 来自第一级的输出信号在第二级中被接收。 第二级产生响应于此的第二级输出。 第二级上拉元件可以由模式信号禁止，期望输入信号将超过第一级，使得第一级上拉元件不会增加第一级输出电压。