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公开(公告)号：US09390944B2
公开(公告)日：2016-07-12
申请号：US14182559
申请日：2014-02-18
IPC分类号： H01L23/48 , H01L21/50 , H01L23/495 , H01L23/482 , H01L23/532 , H01L23/00 , H01L27/088
CPC分类号： H01L23/49562 , H01L21/4825 , H01L21/50 , H01L23/4824 , H01L23/49575 , H01L23/53228 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L27/088 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/97 , H01L2924/1305 , H01L2924/1306 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2924/00
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
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公开(公告)号：US09171743B2
公开(公告)日：2015-10-27
申请号：US14045949
申请日：2013-10-04
IPC分类号： H01L23/48 , H01L21/50 , H01L23/482 , H01L23/495 , H01L25/07
CPC分类号： H01L21/50 , H01L23/4824 , H01L23/49562 , H01L25/072 , H01L2224/16245 , H01L2924/1305 , H01L2924/00
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
摘要翻译： 根据这里的示例性配置，引线框架包括第一导电条，第二导电条和基本相邻并基本上彼此平行设置的第三导电条。 半导体芯片衬底包括与第二阵列开关电路相邻并平行设置的第一开关电路阵列。 第一阵列的开关电路中的源节点被设置为基本上与第二阵列的开关电路中的源节点相邻并且基本上平行。 当半导体芯片和引线框架装置组合以形成电路封装时，电路封装件中的半导体芯片与导电条之间的连接接口将第一阵列的开关电路中的每个源节点与多个源节点 在第二阵列的开关电路中到引线框装置中的公共导电条。
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公开(公告)号：US20140030853A1
公开(公告)日：2014-01-30
申请号：US14045949
申请日：2013-10-04
IPC分类号： H01L21/50
CPC分类号： H01L21/50 , H01L23/4824 , H01L23/49562 , H01L25/072 , H01L2224/16245 , H01L2924/1305 , H01L2924/00
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
摘要翻译： 根据这里的示例性配置，引线框架包括第一导电条，第二导电条和基本相邻并基本上彼此平行设置的第三导电条。 半导体芯片衬底包括与第二阵列开关电路相邻并平行设置的第一开关电路阵列。 第一阵列的开关电路中的源节点被设置为基本上与第二阵列的开关电路中的源节点相邻并且基本上平行。 当半导体芯片和引线框架装置组合以形成电路封装时，电路封装件中的半导体芯片与导电条之间的连接接口将第一阵列的开关电路中的每个源节点与多个源节点 在第二阵列的开关电路中到引线框装置中的公共导电条。
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公开(公告)号：US20100187664A1
公开(公告)日：2010-07-29
申请号：US12505989
申请日：2009-07-20
IPC分类号： H01L23/495 , H01L23/52 , H01L23/48 , H01L21/50
CPC分类号： H01L23/495 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/114 , H01L2224/1146 , H01L2224/1147 , H01L2224/1161 , H01L2224/11848 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/17106 , H01L2224/81191 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/14 , H01L2924/19042 , H01L2924/3011 , H01L2224/29099 , H01L2924/014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.
摘要翻译： 根据这里的示例性配置，引线框架包括连接接口。 连接接口可以被配置为将电路连接到引线框。 引线框架还可以包括导电路径。 引线框架中的导电路径在电路的第一电节点和电路的第二电节点之间提供电连接。 在电路和引线框之间进行连接之前，第一电节点和第二电节点可以彼此电隔离。 在使电路与引线框架连接之后，引线框架的导电路径将第一电节点和第二电节点电连接在一起。 因此，引线框架提供电路的节点之间的连接，代替必须在例如集成电路器件的金属互连层提供这种连接。
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公开(公告)号：US20080204171A1
公开(公告)日：2008-08-28
申请号：US11680323
申请日：2007-02-28
IPC分类号： H03H11/02
CPC分类号： H03H11/48 , H03F3/45183 , H03H11/245
摘要： Methods and apparatus are provided for programmable active inductance. The disclosed active inductor devices provide a tunable bandwidth with improved linearity. The disclosed active inductors have a variable frequency response corresponding to a variable inductance of the active inductor. The active inductor comprises a variable resistive circuit having an effective resistance, wherein the variable resistive circuit is comprised of at least one resistor that can be selectively bypassed in the variable resistive circuit to vary the effective resistive. The active inductor has an inductance that can be varied by varying the effective resistance.
摘要翻译： 为可编程有源电感提供方法和装置。 所公开的有源电感器件提供具有改进的线性度的可调节带宽。 所公开的有源电感器具有对应于有源电感器的可变电感的可变频率响应。 有源电感器包括具有有效电阻的可变电阻电路，其中可变电阻电路包括至少一个可在可变电阻电路中选择性旁路的电阻器，以改变有效电阻。 有源电感器具有可以通过改变有效电阻而变化的电感。
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公开(公告)号：US06909329B2
公开(公告)日：2005-06-21
申请号：US10653630
申请日：2003-09-02
申请人： Hrvoje Jasa , Gary D. Polhemus
发明人： Hrvoje Jasa , Gary D. Polhemus
IPC分类号： H03L7/087 , H03L7/089 , H03L7/091 , H03L7/093 , H03L7/10 , H03L7/113 , H04L7/033 , H03L7/085
CPC分类号： H03L7/087 , H03L7/0893 , H03L7/091 , H03L7/093 , H03L7/10 , H03L7/113 , H03L2207/06 , H04L7/033
摘要： A phase-locked loop (PLL) employs a phase detector (PD) generating an up/down signal based on the phase error between a data signal and a clock signal input to the phase detector. The PD senses excess jitter and extends the loop bandwidth to accommodate such excess jitter. Phase error is derived by sampling of the clock signal and at least one phase-shifted version of the clock signal by the data signal, and a retimed data is generated by the PD by sampling of the data signal by the clock signal. The sampled clocks are employed to generate a modified control signal with greater resolution in detecting the phase error, which, in turn, increases the loop bandwidth.
摘要翻译： 锁相环（PLL）采用基于数据信号和输入到相位检测器的时钟信号之间的相位误差产生上/下信号的相位检测器（PD）。 PD感测到过多的抖动，并扩展了环路带宽以适应这种过多的抖动。 通过数据信号对时钟信号进行采样和时钟信号的至少一个相移版本来导出相位误差，并且通过时钟信号对数据信号进行采样，由PD生成重新定时数据。 采样时钟用于在检测相位误差时产生具有更高分辨率的修正控制信号，进而提高环路带宽。
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公开(公告)号：US5444410A
公开(公告)日：1995-08-22
申请号：US85583
申请日：1993-06-30
申请人： Gary D. Polhemus
发明人： Gary D. Polhemus
IPC分类号： H03K5/01 , H03K5/12 , H03K17/041 , H03K17/14 , H03K17/16 , H04L25/02 , H03K5/08 , H03K17/687 , H03M11/00
CPC分类号： H04L25/0282 , H03K17/04106 , H03K17/145 , H03K17/163 , H03K5/01 , H03K5/12 , H04L25/0274
摘要： A MOS-based current-switch/driver multiplexed and coupled with a tapped delay line so as to form a generator for transmitting on unshielded, unfiltered transmission lines highly-symmetric data pulses displaying minimal transient aberrations and minimal common-mode noise. The switch/driver is a basic differential current switch incorporating two MOS output transistors controlled by a novel switching means. The novel switching means ensures the symmetry of the output signals by compensating for the turn-on/turn-off asymmetries inherent in MOS transistors. The compensation is provided by the control circuit interposed between the switch/driver inputs and the control gates of the output transistors, a control circuit which includes deliberately-skewed CMOS inverters and a pair of MOS driver-transistors associated with each output transistor. The output signals from these current generators are referenced to ground. Transient aberrations are largely eliminated in this invention by lengthening the rise and fall times of the transmitted pulses. A tapped delay line is used in conjunction with a plurality of the new switch/drivers in order to form and transmit composite pulses with rise/fall significantly greater than the natural rise-times and fall-times of the individual switches (about 0.6 nsec).
摘要翻译： MOS基电流开关/驱动器被复用并与抽头延迟线耦合，以便形成用于在非屏蔽的未滤波传输线上传输显示最小瞬变像差和最小共模噪声的高度对称数据脉冲的发生器。 开关/驱动器是包含由新型开关装置控制的两个MOS输出晶体管的基本差分电流开关。 新颖的开关装置通过补偿MOS晶体管固有的导通/关断不对称性来确保输出信号的对称性。 该补偿由插在开关/驱动器输入端和输出晶体管的控制栅极之间的控制电路提供，包括有意倾斜的CMOS反相器的控制电路和与每个输出晶体管相关联的一对MOS驱动器晶体管。 来自这些电流发生器的输出信号参考地。 通过延长发射脉冲的上升和下降时间，在本发明中大部分消除了瞬时像差。 抽头延迟线与多个新的开关/驱动器结合使用，以便形成和传输复合脉冲，其上升/下降明显大于各个开关的自然上升时间和下降时间（约0.6ns） 。
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公开(公告)号：US08648449B2
公开(公告)日：2014-02-11
申请号：US12505989
申请日：2009-07-20
IPC分类号： H01L23/495 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/495 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/114 , H01L2224/1146 , H01L2224/1147 , H01L2224/1161 , H01L2224/11848 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/17106 , H01L2224/81191 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/14 , H01L2924/19042 , H01L2924/3011 , H01L2224/29099 , H01L2924/014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.
摘要翻译： 根据这里的示例性配置，引线框架包括连接接口。 连接接口可以被配置为将电路连接到引线框。 引线框架还可以包括导电路径。 引线框架中的导电路径在电路的第一电节点和电路的第二电节点之间提供电连接。 在电路和引线框之间进行连接之前，第一电节点和第二电节点可以彼此电隔离。 在使电路与引线框架连接之后，引线框架的导电路径将第一电节点和第二电节点电连接在一起。 因此，引线框架提供电路的节点之间的连接，代替必须在例如集成电路器件的金属互连层提供这种连接。
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公开(公告)号：US08022726B2
公开(公告)日：2011-09-20
申请号：US12858990
申请日：2010-08-18
CPC分类号： H02M3/1584 , H02M2001/0012 , H03K19/0002 , H03K19/09425
摘要： A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.
摘要翻译： 控制电路通过将输出编码成具有至少三个状态的多状态信号，来产生基于第一信号和第二信号的输出。 由控制器产生的多态信号的大小根据第一信号和第二信号的二进制状态而变化。 控制器利用输出（即多态信号）来控制开关电路。 驱动电路接收由控制电路产生的输出。 在一个实施例中，多状态信号具有多于两个不同的逻辑状态。 驱动器解码用于产生信号的多态信号以控制开关电路中的开关。 由驱动电路产生的一个信号是脉宽调制信号; 由驱动电路产生的另一信号是使能/禁止信号。
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10.发明授权Apparatus and method for calibrating the frequency of a clock and data recovery circuit 有权用于校准时钟和数据恢复电路的频率的装置和方法公开(公告)号：US07542533B2
公开(公告)日：2009-06-02
申请号：US11176444
申请日：2005-07-07
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/00 , H04L7/0037 , H04L7/0087 , H04L7/027 , H04L7/0276
摘要： Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.
摘要翻译： 本发明的实施例包括用于连续校准时钟和数据恢复（CDR）电路的频率的装置和方法。 该装置包括产生门控信号的延迟装置，以及通过门控信号使能的门控压控振荡器。 门控压控振荡器产生基于输入到CDR电路的数据信号的恢复时钟信号。 该装置还包括一个频率控制回路，其连续校准门控压控振荡器，使得由门控压控振荡器产生的时钟信号的频率继续为数据位的周期的一半 输入数据信号和时钟信号保持与输入数据信号的数据状态转换的中心同步。 或者，次级频率控制环路调整频率控制回路中的延迟量。
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