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    Superconducting Field-Programmable Gate Array
    11.
    发明公开
    Superconducting Field-Programmable Gate Array 审中-公开

    公开(公告)号：US20230283281A1

    公开(公告)日：2023-09-07

    申请号：US18118040

    申请日：2023-03-06

    Applicant: PsiQuantum Corp.

    Inventor： Faraz Najafi

    IPC: H03K19/195 ,  H03K19/17784 ,  H03K19/17736 ,  H03K19/17728

    CPC classification number: H03K19/195 ,  H03K19/17784 ,  H03K19/17744 ,  H03K19/17728

    Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes: (1) a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions, the superconducting component having an input terminal at a first end and an output terminal at a second end opposite of the first end; and (2) control circuitry coupled to the narrow portions of the superconducting component, the control circuitry configured to transition the narrow portions between superconducting and non-superconducting states. In some implementations, the superconducting component and the control circuitry are formed on different layers of the programmable circuit.

    Clock Architecture, including Clock Mesh Fabric, for FPGA, and Method of Operating Same
    13.
    发明申请
    Clock Architecture, including Clock Mesh Fabric, for FPGA, and Method of Operating Same 审中-公开

    公开(公告)号：US20190007047A1

    公开(公告)日：2019-01-03

    申请号：US16009656

    申请日：2018-06-15

    Applicant: Flex Logix Technologies, Inc.

    Inventor： Nitish U. Natu ,  Abhijit M. Abhyankar ,  Cheng C. Wang

    IPC: H03K19/177

    CPC classification number: H03K19/1774 ,  H03K19/17716 ,  H03K19/17724 ,  H03K19/17744

    Abstract: An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.

    Integrated Circuit Including An Array of Logic Tiles, Each Logic Tile Including A Configurable Switch Interconnect Network
    16.
    发明申请
    Integrated Circuit Including An Array of Logic Tiles, Each Logic Tile Including A Configurable Switch Interconnect Network 审中-公开

    公开(公告)号：US20180198450A1

    公开(公告)日：2018-07-12

    申请号：US15898796

    申请日：2018-02-19

    Applicant: Flex Logix Technologies, Inc.

    Inventor： Cheng C. Wang

    IPC: H03K19/177 ,  H03K19/173

    CPC classification number: H03K19/17724 ,  H03K19/1735 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776

    Abstract: An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.

    Methods for memory interface calibration
    20.
    发明授权
    Methods for memory interface calibration 有权

    公开(公告)号：US09911506B1

    公开(公告)日：2018-03-06

    申请号：US15416347

    申请日：2017-01-26

    Applicant: Altera Corporation

    Inventor： Ryan Fung ,  Valavan Manohararajah

    IPC: G11C7/00 ,  G11C29/02

    CPC classification number: G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  H03K5/131 ,  H03K19/17744

    Abstract: Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

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