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162 条记录 (耗时 0.022 秒)

    FUSE CELL STRUCTURE
    14.
    发明公开
    FUSE CELL STRUCTURE 审中-公开

    公开(公告)号：US20230380149A1

    公开(公告)日：2023-11-23

    申请号：US18362290

    申请日：2023-07-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Jhon Jhy Liaw

    IPC分类号： H10B20/20 ,  H01L23/525 ,  G11C17/16

    CPC分类号： H10B20/20 ,  H01L23/5252 ,  G11C17/16

    摘要： A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.

    Vertical fuse memory in one-time program memory cells
    15.
    发明授权
    Vertical fuse memory in one-time program memory cells 有权

    公开(公告)号：US11818882B2

    公开(公告)日：2023-11-14

    申请号：US16885362

    申请日：2020-05-28

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Sheng-Chih Lai ,  Chung-Te Lin

    IPC分类号： G11C17/16 ,  H10B20/20 ,  G11C17/18

    CPC分类号： H10B20/20 ,  G11C17/16 ,  G11C17/18

    摘要： In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.

    INTEGRATED CIRCUIT LAYOUT AND METHOD
    16.
    发明公开
    INTEGRATED CIRCUIT LAYOUT AND METHOD 审中-公开

    公开(公告)号：US20230354591A1

    公开(公告)日：2023-11-02

    申请号：US18346700

    申请日：2023-07-03

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Chien-Ying CHEN ,  Chia-En HUANG ,  Yih WANG

    IPC分类号： H10B20/20 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H10B20/20 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/528

    摘要： A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.

    Vertical fuse memory in one-time program memory cells
    17.
    发明授权
    Vertical fuse memory in one-time program memory cells 有权

    公开(公告)号：US11800703B2

    公开(公告)日：2023-10-24

    申请号：US17880754

    申请日：2022-08-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Sheng-Chih Lai ,  Chung-Te Lin

    IPC分类号： G11C17/16 ,  H10B20/20 ,  G11C17/18

    CPC分类号： H10B20/20 ,  G11C17/16 ,  G11C17/18

    摘要： In some embodiments, the present disclosure relates to a one-time program memory device that includes a source-line arranged over a bottom dielectric layer. Further, a bit-line is arranged directly over the source-line in a first direction. A channel isolation structure is arranged between the source-line and the bit-line. A channel structure is also arranged between the source-line and the bit-line and is arranged beside the channel isolation structure in a second direction perpendicular to the first direction. A vertical gate electrode extends in the first direction from the bottom dielectric layer to the bit-line and is arranged beside the channel isolation structure in the second direction. The one-time program memory device further includes a gate dielectric layer arranged between the vertical gate electrode and the bit-line, the source-line, and the channel structure.

    ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT
    20.
    发明公开
    ONE-TIME PROGRAMMABLE MEMORY DEVICE INCLUDING ANTI-FUSE ELEMENT 审中-公开

    公开(公告)号：US20230284442A1

    公开(公告)日：2023-09-07

    申请号：US18304834

    申请日：2023-04-21

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chiung-Ting OU ,  Ming-Yih WANG ,  Jian-Hong LIN

    IPC分类号： H10B20/20 ,  H01L23/48

    CPC分类号： H10B20/20 ,  H01L23/481

    摘要： A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.