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    Semiconductor device and method of manufacturing the same
    11.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20040164300A1

    公开(公告)日：2004-08-26

    申请号：US10753524

    申请日：2004-01-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japan corporation

    Inventor： Shunpei Yamazaki ,  Hisashi Ohtani

    IPC: H01L031/0328

    CPC classification number: G02F1/136286 ,  G02F1/13454 ,  G11B2220/2545 ,  H01L27/1255 ,  H01L27/1277 ,  H01L29/04 ,  H01L29/045 ,  H01L29/66757 ,  H01L29/78675

    Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.

    Abstract translation: 半导体器件包括根据电路特性设计的TFT。 在本发明的第一结构中，通过使用由独特的晶体结构体制成的晶体硅膜形成TFT。 晶体结构体具有棒状或扁平状的棒状晶体在彼此平行的方向上生长的结构。 在本发明的第二结构中，根据TFT的沟道长度，使横向生长区域的生长距离彼此不同。 由此，可以使形成在一个侧向生长区域中的TFT的特性尽可能均匀。

    NONEQUILIBRIUM PHOTODETECTOR WITH SUPERLATTICE EXCLUSION LAYER
    13.
    发明申请
    NONEQUILIBRIUM PHOTODETECTOR WITH SUPERLATTICE EXCLUSION LAYER 失效
    具有超级排除层的非平衡光电转换器

    公开(公告)号：US20040150002A1

    公开(公告)日：2004-08-05

    申请号：US10354687

    申请日：2003-01-30

    Applicant: SMART PIXEL, INC.

    Inventor： Christoph H. Grein ,  Silviu Velicu ,  Sivalingam Sivananthan

    IPC: H01L027/148 ,  H01L029/768 ,  H01L031/0328 ,  H01L031/0336

    CPC classification number: H01L31/101 ,  B82Y20/00 ,  H01L31/035236 ,  H01L31/1032 ,  H01L31/109

    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. At least one extraction region is disposed on a first side of the active region and has a majority carrier of the second conductivity type. Carriers of the second conductivity type are extracted from the active region and into the extraction region under a condition of reverse bias. At least one exclusion region is disposed on a second side of the active region and has a majority carrier of the first conductivity type. The exclusion region prevents entry of its minority carriers, which are of the second conductivity type, into the active region while in a condition of reverse bias. The exclusion region includes a superlattice with a plurality of layers.

    Abstract translation: 光敏二极管具有限定第一导电类型的多数载流子和第二导电类型的少数载流子的有源区。 至少一个提取区域设置在有源区域的第一侧上并且具有第二导电类型的多数载流子。 第二导电类型的载体在反向偏压的条件下从有源区域提取并进入提取区域。 至少一个排除区域设置在有源区域的第二侧上并且具有第一导电类型的多数载流子。 排斥区域在反向偏压的条件下防止其第二导电类型的少数载流子进入有源区域。 排除区域包括具有多个层的超晶格。

    Semiconductor device and method of manufacturing the same
    15.
    发明申请
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20040113142A1

    公开(公告)日：2004-06-17

    申请号：US10717562

    申请日：2003-11-21

    Applicant: Semiconductor Energy Laboratory Co., Ltd. ,  SHARP KABUSHIKI KAISHA

    Inventor： Akira Ishikawa ,  Yasumori Fukushima

    IPC: H01L029/06 ,  H01L031/0328

    CPC classification number: G02F1/13454 ,  H01L27/124

    Abstract: The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. A semiconductor device according to the present invention is characterized by having a pixel region 1, peripheral circuit regions 2a to 2c arranged in at least a part of the periphery of the pixel region, and a wiring formed in the peripheral circuit region, and by having a wiring multilayered with two or more layers. At least one layer of the multilyered wiring is formed from a low resistance material. Transistors are formed in the peripheral circuit region, and the multilayer wiring with two or more layers is formed on the upper side of the transistors.

    Abstract translation: 本发明提供了一种半导体器件，其中相对于像素区域的外围电路区域的面积减小，并且提供了半导体器件的制造方法。 根据本发明的半导体器件的特征在于，具有像素区域1，配置在像素区域的至少一部分周边的外围电路区域2a〜2c，以及在周边电路区域中形成的布线， 具有两层或多层的多层布线。 多层布线的至少一层由低电阻材料形成。 晶体管形成在外围电路区域中，并且在晶体管的上侧形成具有两层或多层的多层布线。

    Semiconductor device including power MOSFET and peripheral device
    16.
    发明申请
    Semiconductor device including power MOSFET and peripheral device 失效
    半导体器件包括功率MOSFET和外围器件

    公开(公告)号：US20040099922A1

    公开(公告)日：2004-05-27

    申请号：US10621488

    申请日：2003-07-18

    Inventor： Hitoshi Yamaguchi

    IPC: H01L031/0328

    CPC classification number: H01L29/7816 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7801 ,  H01L29/7813 ,  H01L29/7823

    Abstract: First and second trenches are formed on an nnull type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An nnull type epitaxial film, a p type epitaxial film, and an nnull type epitaxial film are deposited on the substrate and in the trenches, and then flattening is performed. As a result, an nnull type region is provided in the second trench of the peripheral device formation region. Then, a p type well layer is formed in the nnull type region by ion-implantation. Accordingly, a power MOSFET and a peripheral device can been formed at the power MOSFET formation region and the peripheral device formation region easily.

    Abstract translation: 第一和第二沟槽分别在功率MOSFET形成区域和外围器件形成区域的n +型衬底上形成。 在衬底上和沟槽中沉积n型外延膜，p型外延膜和n +型外延膜，然后进行平坦化。 结果，在外围器件形成区域的第二沟槽中提供n +型区域。 然后，通过离子注入在n +型区域中形成p型阱层。 因此，能够容易地在功率MOSFET形成区域和外围器件形成区域形成功率MOSFET和外围器件。

    Non-volatile memory device and method for fabricating the same
    18.
    发明申请
    Non-volatile memory device and method for fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20040094776A1

    公开(公告)日：2004-05-20

    申请号：US10704285

    申请日：2003-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

    IPC: H01L031/0328

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

    Abstract translation: 提供了一种非易失性存储器件及其制造方法。 在基板上的有源区上形成浮动区域。 沟槽定义活动区域。 浮动区域由ONO层制成。 在浮动区域上形成栅电极。 在栅电极上形成掩模。 进行热氧化以分别在栅电极和沟槽的侧壁上形成侧壁氧化物和沟槽氧化物。 结果，栅电极和有源区的宽度变得小于浮动区的宽度，从而在浮动区的端部形成突起。 隔离区形成在沟槽中，并且包括侧壁氧化物和沟槽氧化物。 隔离区围绕突起。 结果，在浮动区域的侧壁上感应的电场减小。 此外，热氧化固化对浮动区域的侧壁的任何损坏。 因此，可以在隔离区域和浮动区域之间的边界区域基本上抑制漏电流。

    Voltage level shifter implemented by essentially PMOS transistors
    20.
    发明申请
    Voltage level shifter implemented by essentially PMOS transistors 失效
    基本上由PMOS晶体管实现的电压电平转换器

    公开(公告)号：US20040084696A1

    公开(公告)日：2004-05-06

    申请号：US10692098

    申请日：2003-10-23

    Inventor： Chaung-Ming Chiu

    IPC: H01L031/0328

    CPC classification number: H03K19/01855 ,  G09G2310/0289

    Abstract: A voltage level shifter includes a front stage circuit periodically generating a first control signal and a second control signal in response to a first input clock signal and a second input clock signal complementary to the first input clock signal; a switch circuit including two PMOS transistors connected between a maximum voltage and a minimum voltage in series, wherein a third control signal is outputted from a conjunction of the two PMOS transistors, and the first and second control signals are coupled to the gate electrodes of the two PMOS transistors, respectively; and a driving circuit receiving the third control signal and outputting an output clock signal having a peak-to-peak value larger than a peak-to-peak value of the input clock signal. The voltage level shifter is implemented by essentially PMOS transistors.

    Abstract translation: 电压电平移位器包括响应于与第一输入时钟信号互补的第一输入时钟信号和第二输入时钟信号周期性地产生第一控制信号和第二控制信号的前级电路; 包括连接在最大电压和最小电压串联的两个PMOS晶体管的开关电路，其中从两个PMOS晶体管的结合输出第三控制信号，并且第一和第二控制信号耦合到 两个PMOS晶体管; 以及驱动电路，接收第三控制信号并输出​​具有大于输入时钟信号的峰 - 峰值的峰峰值的输出时钟信号。 电压电平移位器基本上由PMOS晶体管实现。

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