Systems and methods for micromechanical displacement-based logic circuits

    公开(公告)号:US10855259B1

    公开(公告)日:2020-12-01

    申请号:US16808629

    申请日:2020-03-04

    IPC分类号: H03K3/037 B81B3/00 H03K3/013

    摘要: The present disclosure relates to a micromechanical displacement logic, signal propagation system that makes use of first and second bistable elements, and first and second mounting structures arranged adjacent opposing surfaces of the first bistable element. A plurality of pivotal lever arms are used to support the first bistable element in either one of two positions of equilibrium. A support structure and a compressible flexure element disposed between the support structure and the first mounting structure apply a preload force to the first mounting structure, which imparts the preload force to the first bistable element. The first bistable element is moveable from one of the two stable equilibrium positions to the other in response to an initial signal applied thereto. The preload force, at least one stiffness characteristic of the lever arms, and a compressibility of a compressible coupling element which links the second bistable element to the first, are all selected to tune signal propagation from the first bistable element to the second bistable element.

    SYSTEM AND METHOD OF DUPLICATE CIRCUIT BLOCK SWAPPING FOR NOISE REDUCTION

    公开(公告)号:US20200328731A1

    公开(公告)日:2020-10-15

    申请号:US16912652

    申请日:2020-06-25

    IPC分类号: H03K3/013

    摘要: An integrated circuit including a functional circuit including at least one swapping circuit node, multiple duplicate electronic circuits, and a switch circuit. The duplicate electronic circuits are integrated in close proximity with each other each including at least one electronic device that is susceptible to RTN. The switch circuit electrically couples a different selected subset of at least one of the duplicate electronic circuits to the at least one swapping circuit node for each of successive switching states during operation of the functional circuit. A method of reducing noise including selecting a subset of the duplicate electronic circuits, electrically coupling the selected duplicate electronic devices to at least one swapping circuit node of a functional circuit, and repeating the selecting and electrically coupling in successive switching states during operation of the functional circuit for different subsets of the duplicate electronic circuits.

    Low power flip-flop circuit
    13.
    发明授权

    公开(公告)号:US10715119B2

    公开(公告)日:2020-07-14

    申请号:US16431692

    申请日:2019-06-04

    发明人: Mingming Mao

    摘要: Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a passgate, a passgate inverter, a leakage compensation unit, and an inverter. The passgate may be coupled between a flip-flop data input terminal and a first node. The passgate inverter and the inverter may be sequentially connected between the first node and a flip-flop data output terminal. The leakage compensation unit may be connected between the first node and the flip-flop data output terminal parallel to the passgate inverter and the inverter.

    MIXED SIGNAL CIRCUIT SPUR CANCELLATION
    14.
    发明申请

    公开(公告)号:US20200177168A1

    公开(公告)日:2020-06-04

    申请号:US16396873

    申请日:2019-04-29

    IPC分类号: H03K3/013 H03K21/10 H03K3/037

    摘要: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.

    Relaxation oscillator and wireless device including relaxation oscillator

    公开(公告)号:US10581411B2

    公开(公告)日:2020-03-03

    申请号:US15992870

    申请日:2018-05-30

    申请人: ABLIC Inc.

    摘要: Provided is a relaxation oscillator having an extremely small temperature deviation in oscillation frequency. A first current (I1) generated by a reference voltage source and a first resistor having a positive first-order temperature coefficient is supplied to a first variable capacitor (C1) for oscillation, and a second current (I2) generated by a reference voltage source and a second resistor having a negative first-order temperature coefficient is supplied to a second variable capacitor (C2) for oscillation. A product of a value of a ratio of a first current to a second current and a value of a ratio of a first-order temperature coefficient of the second resistor to a first-order temperature coefficient of the first resistor, and a value of a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor have the same absolute value and opposite signs.

    HIGH SIDE SIGNAL INTERFACE IN A POWER CONVERTER

    公开(公告)号:US20200067415A1

    公开(公告)日:2020-02-27

    申请号:US16664475

    申请日:2019-10-25

    摘要: A method to control a high side switch of a motor drive includes sinking a current of an ON signal to communicate a turn ON of the high side switch. A first current signal, a second current signal, a third current signal, a fourth current signal and a common mode rejection signal are generated in response to the ON signal. The ON signal in a presence of common mode noise is determined by comparing the first current signal and the second current signal. A first output signal is generated in response to determining the ON signal. A drive signal is generated responsive to the first output signal to control the high side switch in response to the ON signal in presence of common mode noise that is caused by a slewing at a half-bridge node.

    Reduction and/or mitigation of crosstalk in quantum bit gates

    公开(公告)号:US10546244B2

    公开(公告)日:2020-01-28

    申请号:US16255454

    申请日:2019-01-23

    IPC分类号: G06N10/00 H03K3/013 H03K3/38

    摘要: Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.

    Self-injection locking for low-power low-phase noise oscillators

    公开(公告)号:US10541697B2

    公开(公告)日:2020-01-21

    申请号:US15690117

    申请日:2017-08-29

    摘要: For producing a low-power, low-phase noise oscillating signal using a self-injection locking oscillator, examples include: producing, using an oscillator, a signal having a base frequency component and an Nth harmonic component, in which N is a selected integer and N>1; filtering the signal through a bandpass filter with Q factor ≥5, the filter configured to pass the Nth harmonic component as a filtered Nth harmonic component; and injecting the filtered Nth harmonic component into the oscillator to self-injection lock the base frequency of the signal.

    Techniques for detecting and correcting errors on a ring oscillator

    公开(公告)号:US10483951B2

    公开(公告)日:2019-11-19

    申请号:US15693440

    申请日:2017-08-31

    摘要: A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.