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267 条记录 (耗时 0.027 秒)

    FM reception device, FM reception method for receiving FM signals
    12.
    发明授权
    FM reception device, FM reception method for receiving FM signals 有权

    公开(公告)号：US10270483B2

    公开(公告)日：2019-04-23

    申请号：US15635437

    申请日：2017-06-28

    申请人： JVC KENWOOD Corporation

    发明人： Yasuhide Okuhata

    IPC分类号： H04B1/10 ,  H04B1/30 ,  H04L27/00 ,  H04L27/14 ,  H04L27/16 ,  H04L27/152

    摘要： A quadrature detection unit subjects an FM signal to quadrature detection using a local oscillation signal and outputs a base band signal. A first correction unit and a second correction unit correct the base band signal using a DC offset correction value. A DC offset detection unit subjects the corrected base band signal to rectangular to polar conversion and derives the DC offset correction value such that amplitudes in a plurality of phase domains defined in an IQ plane approximate each other. An FM detection unit subjects the corrected base band signal to FM detection and generates a detection signal. An addition unit adds an offset to the detection signal. An AFC unit generates a control signal for controlling a frequency of a local oscillation signal based on the detection signal to which the offset is added.

    TRANSMITTER PERFORMANCE CALIBRATION SYSTEMS AND METHODS
    14.
    发明申请
    TRANSMITTER PERFORMANCE CALIBRATION SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20180091241A1

    公开(公告)日：2018-03-29

    申请号：US15276009

    申请日：2016-09-26

    申请人： INTEL IP CORPORATION

    发明人： Franz Kuttner

    IPC分类号： H04B17/14 ,  H04L27/152

    CPC分类号： H04B17/14 ,  H04B1/525 ,  H04B2001/0408 ,  H04L27/152

    摘要： An apparatus is disclosed that includes a transmit chain, a duplexer, a receive chain and a control circuit. The transmit chain is configured to generate a transmit signal at a transmit frequency. The duplexer is configured to pass the transmit signal to an antenna that generates a transmit leakage current into a received signal. The receive chain is configured to obtain the received signal and measure the leakage current from the transmit chain. The control circuit is configured to determine reduced performance parameters for the transmit chain based on the determined leakage signal, wherein the transmit leakage signal is inversely proportional to the reduced performance parameters.

    On-chip jitter measurement for clock circuits
    15.
    发明授权
    On-chip jitter measurement for clock circuits 有权

    公开(公告)号：US09893878B1

    公开(公告)日：2018-02-13

    申请号：US15459715

    申请日：2017-03-15

    申请人： Oracle International Corporation

    发明人： Long Kong ,  Ben Li Chen ,  Philip Kwan ,  Zuxu Qin ,  Dawei Huang

    IPC分类号： H04L27/152 ,  H04L7/033 ,  H03L7/089 ,  H03L7/099 ,  H03L7/081 ,  H04L7/00

    CPC分类号： H04L1/20 ,  H03L7/08

    摘要： Embodiments include systems and methods for on-chip random jitter (RJ) measurement in a clocking circuit (e.g., in a phase-locked loop of a serializer/deserializer circuit). Some embodiments determine a reference delay code sweep window to capture at least a candidate RJ range of a feedback clock signal, the reference delay code sweep window comprising a sequence of reference delay codes. A distribution of one-scores can be computed over the reference delay code sweep window, so that the distribution indicates a relatively likelihood, for each reference delay code, of obtaining a ‘1’ sample when sampling the feedback clock signal according to the delayed clock signal (delayed by an amount according to the reference delay code). The distribution can be transformed into a time domain by computing code offset times for the reference delay codes. A RJ output can be computed as a function of the distribution in the time domain.

    Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces
    16.
    发明授权
    Link training to recover asynchronous clock timing margin loss in parallel input/output interfaces 有权

    公开(公告)号：US09742603B1

    公开(公告)日：2017-08-22

    申请号：US15363075

    申请日：2016-11-29

    申请人： INTEL CORPORATION

    发明人： Chenchu Punnarao Bandi ,  Amit Kumar Srivastava ,  Sabyasachi Mohapatra

    IPC分类号： H03D3/24 ,  H04L27/152 ,  H04L7/00 ,  H04L7/033

    CPC分类号： H04L7/10 ,  H04L7/0091

    摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal.

    Frequency control circuit, frequency control method and phase locked loop circuit
    17.
    发明授权
    Frequency control circuit, frequency control method and phase locked loop circuit 有权

    公开(公告)号：US09722832B1

    公开(公告)日：2017-08-01

    申请号：US15191509

    申请日：2016-06-23

    申请人： HIMAX TECHNOLOGIES LIMITED

    发明人： Shih-Che Hung ,  Chun-Liang Chen

    IPC分类号： H04L27/152 ,  H04L7/033

    CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099 ,  H03L7/113 ,  H04L27/0014 ,  H04L2027/0067

    摘要： A frequency control circuit, adapted to be utilized in a phase locked loop circuit. The frequency control circuit includes a first frequency control block, a second frequency control block, a pump control unit and a charge pump unit. The first frequency control block generates a first control signal according to a frequency of an output signal from the phase locked loop circuit, in which the first control signal is configured to control the frequency of the output signal located within a predetermined frequency region. The second frequency control block generates a second control signal according to a frequency of an input signal and the frequency of the output signal, in which the second control signal is configured to control the frequency of the output signal located at a target frequency.

    Phase-locked loop frequency calibration method and system
    20.
    发明授权
    Phase-locked loop frequency calibration method and system 有权
    锁相环频率校准方法和系统

    公开(公告)号：US09455854B2

    公开(公告)日：2016-09-27

    申请号：US14730008

    申请日：2015-06-03

    申请人： Huawei Technologies Co., Ltd.

    发明人： Peng Gao ,  Nianyong Zhu ,  Jian Liang

    IPC分类号： H04L27/152 ,  H04L7/033 ,  H04B17/21 ,  H04B1/16 ,  H03L7/18 ,  H04B17/14

    CPC分类号： H04L27/152 ,  H03L7/18 ,  H04B1/16 ,  H04B17/14 ,  H04B17/21 ,  H04L7/0331

    摘要： The present invention provides a phase-locked loop frequency calibration method and system, where the method includes: performing, within a counting time TCNT[k], frequency counting on a frequency signal that is output in a current working subband by a voltage-controlled oscillator, to obtain a frequency count value FCNT[k], where the current working subband corresponds to a binary value of a current node in a binary search tree; and calculating an error between FCNT[k] and a target frequency count value FCNTTARGET[k], comparing an absolute value of the error with a predetermined value, dynamically adjusting TCNT[k] in a value range of TCNT[k] according to a comparison result, and determining, in combination with a binary search algorithm, a target subband in which the voltage-controlled oscillator works. Such a dynamic calibration method can effectively shorten the calibration time on the whole.

    摘要翻译： 本发明提供了一种锁相环频率校准方法和系统，其中该方法包括：在计数时间TCNT [k]内，对通过电压控制的当前工作子带中输出的频率信号进行频率计数 振荡器，以获得频率计数值FCNT [k]，其中当前工作子带对应于二叉搜索树中当前节点的二进制值; 并计算FCNT [k]与目标频率计数值FCNTTARGET [k]之间的误差，将误差的绝对值与预定值进行比较，根据TCNT [k]在TCNT [k]的值范围内动态调整TCNT [k] 比较结果，并结合二进制搜索算法确定压控振荡器工作的目标子带。 这种动态校准方法可以有效地缩短整个校准时间。