公开(公告)号：US10651869B1

公开(公告)日：2020-05-12

申请号：US16364891

申请日：2019-03-26

Applicant: Intel IP Corporation ,  Intel Corporation

Inventor： Davide Ponton ,  Michael Kalcher ,  Alan Paussa ,  Edwin Thaller ,  Franz Kuttner ,  Daniel Gruber

IPC: H03M1/48 ,  H03M1/66 ,  H04B1/403 ,  H04B1/401 ,  H04B1/04

Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

公开(公告)号：US10332871B2

公开(公告)日：2019-06-25

申请号：US15073950

申请日：2016-03-18

Applicant: Intel IP Corporation

Inventor： Christian Cornelius Russ ,  Giuseppe Curello ,  Tomasz Biedrzycki ,  Franz Kuttner ,  Luis F. Giles ,  Bernhard Stein

IPC: H01L27/02 ,  H01L23/367 ,  H01L23/50 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L27/092 ,  H02H9/04

Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

公开(公告)号：US20180091241A1

公开(公告)日：2018-03-29

申请号：US15276009

申请日：2016-09-26

Applicant: INTEL IP CORPORATION

Inventor： Franz Kuttner

IPC: H04B17/14 ,  H04L27/152

CPC classification number: H04B17/14 ,  H04B1/525 ,  H04B2001/0408 ,  H04L27/152

Abstract: An apparatus is disclosed that includes a transmit chain, a duplexer, a receive chain and a control circuit. The transmit chain is configured to generate a transmit signal at a transmit frequency. The duplexer is configured to pass the transmit signal to an antenna that generates a transmit leakage current into a received signal. The receive chain is configured to obtain the received signal and measure the leakage current from the transmit chain. The control circuit is configured to determine reduced performance parameters for the transmit chain based on the determined leakage signal, wherein the transmit leakage signal is inversely proportional to the reduced performance parameters.

公开(公告)号：US10122477B2

公开(公告)日：2018-11-06

申请号：US15276009

申请日：2016-09-26

Applicant: INTEL IP CORPORATION

Inventor： Franz Kuttner

IPC: H03C1/62 ,  H04B17/14 ,  H04L27/152 ,  H04B1/525 ,  H04B1/04

Abstract: An apparatus is disclosed that includes a transmit chain, a duplexer, a receive chain and a control circuit. The transmit chain is configured to generate a transmit signal at a transmit frequency. The duplexer is configured to pass the transmit signal to an antenna that generates a transmit leakage current into a received signal. The receive chain is configured to obtain the received signal and measure the leakage current from the transmit chain. The control circuit is configured to determine reduced performance parameters for the transmit chain based on the determined leakage signal, wherein the transmit leakage signal is inversely proportional to the reduced performance parameters.

公开(公告)号：US09985811B2

公开(公告)日：2018-05-29

申请号：US15274721

申请日：2016-09-23

Applicant: Intel IP Corporation

Inventor： Christian Mayer ,  Franz Kuttner

IPC: H04B1/04 ,  H04L27/08 ,  H04B1/00

CPC classification number: H04L27/08 ,  H04B1/0042 ,  H04B1/04 ,  H04L27/2614

Abstract: Disclosed herein is an apparatus and methodology for reducing peak-to-average-power ratio (PAPR) for IQ radio frequency digital-to-analog converter (RFDAC). Processing circuitry may be configured to generate a digital signal comprising an in-phase (I) signal component and a quadrature (Q) signal component having a peak-to-average-power-ratio (PAPR). The processing circuitry may determine the I signal component and the Q signal component are higher than a predetermined threshold value, and limit the I signal component and the Q signal component to be less than or equal to the predetermined threshold value. The processing circuitry may rotate the signal components to generate rotated signal components to reduce the PAPR based on the I and Q signal components having less than or equal to the predetermined threshold value, and may generate an output radio frequency (RF) signal based on the rotated signal components.

公开(公告)号：US20170271322A1

公开(公告)日：2017-09-21

申请号：US15073950

申请日：2016-03-18

Applicant: Intel IP Corporation

Inventor： Christian Cornelius Russ ,  Giuseppe Curello ,  Tomasz Biedrzycki ,  Franz Kuttner ,  Luis F. Giles ,  Bernhard Stein

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/367 ,  H01L27/06 ,  H01L23/522 ,  H02H9/04 ,  H01L23/50

CPC classification number: H01L27/0285 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0924 ,  H01L28/00 ,  H02H9/046

Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

公开(公告)号：US09647678B2

公开(公告)日：2017-05-09

申请号：US15240462

申请日：2016-08-18

Applicant: Intel IP Corporation

Inventor： Antonio Passamani ,  Franz Kuttner ,  Michael Fulde

IPC: H03M1/66 ,  H04L27/00 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03M1/74 ,  H04L27/00 ,  H04L27/0002

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

公开(公告)号：US20170093422A1

公开(公告)日：2017-03-30

申请号：US15240462

申请日：2016-08-18

Applicant: Intel IP Corporation

Inventor： Antonio Passamani ,  Franz Kuttner ,  Michael FULDE

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/74 ,  H04L27/00 ,  H04L27/0002

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

公开(公告)号：US09571120B2

公开(公告)日：2017-02-14

申请号：US14835031

申请日：2015-08-25

Applicant: Intel IP Corporation

Inventor： Franz Kuttner ,  Antonio Passamani ,  Davide Ponton

IPC: H03M1/66 ,  H03M1/74 ,  H03M1/00 ,  H03M1/12 ,  H03M3/00

CPC classification number: H03M1/662 ,  H03M1/00 ,  H03M1/12 ,  H03M1/74 ,  H03M1/747 ,  H03M3/30

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract translation: 数模转换器电路包括多个数模转换器单元。 数模转换器电路还包括控制电路，其被配置为基于数字信号的第一相位分量来控制多个数模转换器单元中的数模转换器单元的操作，该数字信号包括将在第一 时间间隔，并且基于数字信号的第二相位分量，包括将在第二时间间隔期间发送的信息。

公开(公告)号：US20160094235A1

公开(公告)日：2016-03-31

申请号：US14835031

申请日：2015-08-25

Applicant: Intel IP Corporation

Inventor： Franz Kuttner ,  Antonio Passamani ,  Davide Ponton

IPC: H03M1/00 ,  H03M1/74

CPC classification number: H03M1/662 ,  H03M1/00 ,  H03M1/12 ,  H03M1/74 ,  H03M1/747 ,  H03M3/30

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract translation: 数模转换器电路包括多个数模转换器单元。 数模转换器电路还包括控制电路，其被配置为基于数字信号的第一相位分量来控制多个数模转换器单元中的数模转换器单元的操作，该数字信号包括将在第一 时间间隔，并且基于数字信号的第二相位分量，包括将在第二时间间隔期间发送的信息。