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公开(公告)号：US20240427094A1
公开(公告)日：2024-12-26
申请号：US18212754
申请日：2023-06-22
Applicant: GlobalFoundries U.S. Inc.
Inventor： Keith Donegan , Takako Hirokawa , Yusheng Bian , Thomas Houghton , Kevin Dezfulian , Carrie Yurkon
Abstract: Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.
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192.发明授权公开(公告)号：US12176351B2
公开(公告)日：2024-12-24
申请号：US17973618
申请日：2022-10-26
Applicant: GlobalFoundries U.S. Inc.
Inventor： Ryan Sporer , George R. Mulfinger , Yusheng Bian
IPC: H01L27/12 , H01L21/762 , H01L21/84 , H01L27/146 , H01L29/06
Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.
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193.发明申请公开(公告)号：US20240419023A1
公开(公告)日：2024-12-19
申请号：US18209680
申请日：2023-06-14
Applicant: GlobalFoundries U.S. Inc.
Inventor： Yusheng Bian
IPC: G02F1/035
Abstract: Photonics chip structures including an edge coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a substrate, an edge coupler on the substrate, and a layer including a portion that has an overlapping relationship with the edge coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.
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194.发明申请公开(公告)号：US20240402421A1
公开(公告)日：2024-12-05
申请号：US18802210
申请日：2024-08-13
Applicant: GlobalFoundries U.S. Inc.
Inventor： Nicholas A. Polomoff , Thomas Houghton , Yusheng Bian
Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.
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公开(公告)号：US20240377583A1
公开(公告)日：2024-11-14
申请号：US18196796
申请日：2023-05-12
Applicant: GlobalFoundries U.S. Inc.
Inventor： Yusheng Bian
Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer on the pad, a first waveguide core including a tapered section adjacent to a sidewall of the semiconductor layer, and a second waveguide core including a curved section adjacent to the sidewall of the semiconductor layer. The curved section includes a plurality of segments, and the tapered section of the first waveguide core is overlapped by at least one of the plurality of segments in the curved section of the second waveguide core.
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Patent Agency Ranking
公开(公告)号：US20240348005A1
公开(公告)日：2024-10-17
申请号：US18134068
申请日：2023-04-13
Applicant: GlobalFoundries U.S. Inc.
Inventor： Zhuojie Wu , Yusheng Bian , Koushik Ramachandran
IPC: H01S5/024 , G02B6/42 , H01S5/02345 , H01S5/0236 , H01S5/0237 , H01S5/183
CPC classification number: H01S5/02469 , G02B6/4215 , H01S5/02345 , H01S5/0236 , H01S5/0237 , H01S5/18305
Abstract: Structures including a photonics chip and a surface-mounted laser chip, and methods of forming same. The structure comprises a photonics chip including a surface, a laser chip including a light output and a body that are spaced from the surface of the photonics chip, a first adhesive between the body of the laser chip and the surface of the photonics chip, and a second adhesive between the body of the laser chip and the surface of the photonics chip. The light output is oriented toward the surface of the photonics chip, the first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity that is less than the first thermal conductivity of the first adhesive, and the second adhesive is disposed in a light path between the light output of the laser chip and the surface of the photonics chip.
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公开(公告)号：US20240329308A1
公开(公告)日：2024-10-03
申请号：US18127220
申请日：2023-03-28
Applicant: GlobalFoundries U.S. Inc.
Inventor： Arpan Dasgupta , Yusheng Bian , John M. Safran , Norman Robson
CPC classification number: G02B6/1228 , G02B6/13
Abstract: Structures including multiple photonics chips and methods of fabricating a structure including multiple photonics chips. The structure comprises a first chip including a first edge and a first plurality of optical couplers disposed at the first edge, and a second chip including a second edge adjacent to the first edge of the first chip and a second plurality of optical couplers. The second plurality of optical couplers are disposed at the second edge adjacent to the first plurality of optical couplers.
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198.发明公开公开(公告)号：US20240241313A1
公开(公告)日：2024-07-18
申请号：US18619985
申请日：2024-03-28
Applicant: GlobalFoundries U.S. Inc.
Inventor： Yusheng Bian
CPC classification number: G02B6/1228 , G02B6/126
Abstract: Disclosed is a structure including a polarization device with first and second waveguides. The first waveguide includes a core (e.g., a silicon nitride (SiN) core) suitable for high-power applications. The second waveguide includes: a primary core (e.g., another SiN core), which is positioned laterally adjacent to the core of the first waveguide and suitable for high-power applications, and secondary core(s) stacked vertically with the primary core to steer the optical mode and ensure that mode matching occurs between adjacent first and second coupling sections of the first and second waveguides, respectively, in order to achieve high-power splitter and/or combiner functions. Optionally, the primary and secondary cores of the second waveguide can be tapered at least within the second coupling section to increase the likelihood of mode matching.
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公开(公告)号：US12038615B2
公开(公告)日：2024-07-16
申请号：US17701918
申请日：2022-03-23
Applicant: GlobalFoundries U.S. Inc.
Inventor： Yusheng Bian
IPC: G02B6/42
CPC classification number: G02B6/4203 , G02B6/42
Abstract: Structures for an edge coupler and methods of fabricating such structures. The structure includes a substrate, a first waveguide core, and a second waveguide core positioned in a vertical direction between the first waveguide core and the substrate. The second waveguide core includes a taper and an inverse taper longitudinally positioned adjacent to the taper.
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公开(公告)号：US12001056B2
公开(公告)日：2024-06-04
申请号：US17834375
申请日：2022-06-07
Applicant: GlobalFoundries U.S. Inc.
Inventor： Bartlomiej Jan Pawlak , Michal Rakowski , Yusheng Bian
CPC classification number: G02B6/2934 , G02B6/4215
Abstract: Structures including stacked photonics chips and methods of fabricating a structure including stacked photonics chips. The structure comprises a first chip including a first waveguide core, a ring resonator adjacent to a portion of the first waveguide core, and a first dielectric layer over the first waveguide core and the ring resonator. The first dielectric layer has a first surface. The structure further comprises a second chip including a second waveguide core and a second dielectric layer over the second waveguide core. The second dielectric layer has a second surface adjacent to the first surface of the first dielectric layer, and the second waveguide core is positioned adjacent to the ring resonator.
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