公开(公告)号：US20230017388A1

公开(公告)日：2023-01-19

申请号：US17873850

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Micheie Piccardi ,  Qing Liang

IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US20220350532A1

公开(公告)日：2022-11-03

申请号：US17243321

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Nadav Grosz ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.

公开(公告)号：US20220350504A1

公开(公告)日：2022-11-03

申请号：US17729207

申请日：2022-04-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Xiaojiang Guo

IPC: G06F3/06

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

公开(公告)号：US20220300208A1

公开(公告)日：2022-09-22

申请号：US17631201

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Jingyuan Miao ,  Bin Zhao

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory read performance techniques are described. A memory system may receive a sequence of read commands. Based on detecting a set of consecutive read commands, the memory system may pre-read data from a second logical block address (LBA) in a non-volatile memory device to a volatile memory device based on receiving a first read command that includes a first LBA, where the second LBA is consecutive with the first LBA. The memory system may subsequently receive a second read command that includes the second LBA, and read out the second data without performing an additional access operation of the non-volatile storage device. In some examples, using such a pre-read, the memory system may capable of returning data in a different order than the order in which the commands were received.

公开(公告)号：US20220300179A1

公开(公告)日：2022-09-22

申请号：US17648399

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

公开(公告)号：US20220254434A1

公开(公告)日：2022-08-11

申请号：US17574024

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Chun S. Yeung ,  Deping He ,  Jonathan S. Parry

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/04

Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

公开(公告)号：US11294838B2

公开(公告)日：2022-04-05

申请号：US16942564

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Stephen D. Hanna ,  Jonathan S. Parry

IPC: G06F13/40 ,  G06F1/26

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

公开(公告)号：US20220035758A1

公开(公告)日：2022-02-03

申请号：US16942564

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Stephen D. Hanna ,  Jonathan S. Parry

IPC: G06F13/40 ,  G06F1/26

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

公开(公告)号：US11237612B2

公开(公告)日：2022-02-01

申请号：US16548639

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/26 ,  G06F1/32 ,  G11C5/14 ,  G11C11/4074 ,  H01L23/00 ,  G06F1/3225 ,  G06F1/3212 ,  G06F1/3234

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US20210373939A1

公开(公告)日：2021-12-02

申请号：US16889029

申请日：2020-06-01

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Kulachet Tanpairoj ,  Stephen Hanna

IPC: G06F9/48 ,  G06F12/0875

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.