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公开(公告)号：US20190189206A1
公开(公告)日：2019-06-20
申请号：US15842504
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C2013/0052 , G11C2013/0092 , G11C2213/30 , G11C2213/71 , H01L27/2463 , H01L45/1253 , H01L45/141
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20190156885A1
公开(公告)日：2019-05-23
申请号：US16185154
申请日：2018-11-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
CPC classification number: G11C13/0004 , G11C11/005 , G11C11/5678 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/73 , G11C2213/77
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US20190156884A1
公开(公告)日：2019-05-23
申请号：US16185146
申请日：2018-11-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
CPC classification number: G11C13/0004 , G11C11/005 , G11C11/5678 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/73 , G11C2213/77
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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公开(公告)号：US10263039B2
公开(公告)日：2019-04-16
申请号：US15632536
申请日：2017-06-26
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20180374900A1
公开(公告)日：2018-12-27
申请号：US15632536
申请日：2017-06-26
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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Patent Agency Ranking
公开(公告)号：US10163506B2
公开(公告)日：2018-12-25
申请号：US15841118
申请日：2017-12-13
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Innocenzo Tortorelli , Andrea Redaelli , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
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公开(公告)号：US10128437B1
公开(公告)日：2018-11-13
申请号：US15692387
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Agostino Pirovano
Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.
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公开(公告)号：US09893279B2
公开(公告)日：2018-02-13
申请号：US15438499
申请日：2017-02-21
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto M. Meotto
CPC classification number: H01L45/1286 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C13/04 , G11C2013/008 , G11C2213/56 , G11C2213/76 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1608
Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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公开(公告)号：US20160254050A1
公开(公告)日：2016-09-01
申请号：US15154410
申请日：2016-05-13
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Davide Fugazza , Johannes A. Kalb
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.
Abstract translation: 本文公开的各种实施例包括用于将存储器阵列的相变存储器（PCM）单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。 在一个实施例中，该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置，其中成核信号具有非零上升沿。 随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。 还描述了附加的方法和装置。
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公开(公告)号：US20140209848A1
公开(公告)日：2014-07-31
申请号：US14242706
申请日：2014-04-01
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L27/2445 , H01L45/00 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/144
Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.
Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。
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