公开(公告)号：US20230343394A1

公开(公告)日：2023-10-26

申请号：US17727515

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/5226 ,  H01L23/5283

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.

公开(公告)号：US11791268B2

公开(公告)日：2023-10-17

申请号：US17666093

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Travis Rampton ,  Everett Allen McTeer ,  Rita J. Klein

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53257 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

公开(公告)号：US20230262976A1

公开(公告)日：2023-08-17

申请号：US17674289

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/0483

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers having channel-material strings therein. Walls are formed above insulating material that is directly above the channel-material strings. Void space is laterally-between immediately-adjacent of the walls and that comprises a longitudinal outline of individual digitlines to be formed. Spaced openings are in the insulating material directly below the void space. Relative to the walls, a conductive metal nitride is selectively deposited in the void space, in the spaced openings, and atop the insulating material laterally-between the walls and the spaced openings to form a lower portion of the individual digitlines laterally-between the immediately-adjacent walls. The conductive metal nitride that is in individual of the spaced openings is directly electrically coupled to individual of the channel-material strings. A conductive material is formed in the void space directly above and directly electrically coupled to the lower portion of the individual digitlines to form an upper portion thereof. Other embodiments, including structure independent of method, are disclosed,

公开(公告)号：US11715692B2

公开(公告)日：2023-08-01

申请号：US16990580

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Francois H. Fabreguette ,  John A. Smythe

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5286 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/53266 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230209831A1

公开(公告)日：2023-06-29

申请号：US17658778

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device includes a source stack, a source contact vertically adjacent to the source stack, a semiconductor material vertically adjacent to the source contact, tiers of alternating conductive materials and dielectric materials vertically adjacent to the semiconductor dielectric material, a dielectric structure within a slot structure and extending through the tiers of the microelectronic device to the source contact of the microelectronic device, oxide cap structures laterally between the semiconductor material and the dielectric structure, and pillars extending through the tiers, the semiconductor material, and the source contact and into the source stack. Related electronic systems and methods are also disclosed.

公开(公告)号：US20230121315A1

公开(公告)日：2023-04-20

申请号：US18083428

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H10B41/27

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20230116988A1

公开(公告)日：2023-04-20

申请号：US18083431

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Peng Xu

IPC: G11C5/06 ,  H10B41/35 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/41 ,  C23C8/06 ,  C23C8/36 ,  C23C28/00

Abstract: Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed over a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. The exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. Some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. The first region has a greater concentration of one or both of fluorine and boron relative to the second region.

公开(公告)号：US20230099418A1

公开(公告)日：2023-03-30

申请号：US18076702

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  G11C16/04

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230061327A1

公开(公告)日：2023-03-02

申请号：US18047245

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11575

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20230055422A1

公开(公告)日：2023-02-23

申请号：US17409476

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.