公开(公告)号：US20240411563A1

公开(公告)日：2024-12-12

申请号：US18809646

申请日：2024-08-20

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  G06F12/14 ,  G06F21/57 ,  G06F21/78 ,  H04L9/32

Abstract: An example device includes a first interface configured to couple to a first memory that is configured to store an image that includes a set of slices; a second interface configured to couple to a second memory; and a direct memory access circuit coupled to the first and second interfaces. The direct memory access circuit receives a transaction that specifies a read of a slice of the set of slices; and based on the transaction, reads the slice from the first memory; performs operations to the slice; and stores the slice in the second memory.

公开(公告)号：US12131504B2

公开(公告)日：2024-10-29

申请号：US17538268

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

IPC: G06K9/00 ,  G06T1/20 ,  G06T7/90

CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/10024 ,  G06T2207/20208

Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

公开(公告)号：US12126549B2

公开(公告)日：2024-10-22

申请号：US18357710

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

IPC: H04L49/90 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

CPC classification number: H04L49/9042 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

Abstract: In an example, a system includes a network port that receives a packet; a first memory; a second memory; and a packet analyzer coupled to the network port. The packet analyzer operates to divide the packet into multiple fragments, analyze each of the multiple fragments to determine whether the corresponding fragment has a first priority level or a second, lower, priority level, determine whether to store each of the multiple fragments in the first memory or the second memory based on the priority level determined for that fragment, store each fragment determined to have the first priority level in the first memory, and store each fragment determined to have the second priority level in the second memory. The network port, packet analyzer and the first memory, which may be a cache memory, may be embodied on a chip, and the second memory may be external to the chip.

公开(公告)号：US20240345870A1

公开(公告)日：2024-10-17

申请号：US18748423

申请日：2024-06-20

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: Systems and method are provided for flexibly configuring task schedulers and respectively associated data processing nodes to execute threads of tasks using a hardware thread scheduler (HTS). The data processing nodes may be hardware accelerators, channels of a direct memory access circuit and external nodes such as a processor executing software instructions. Each hardware accelerator is coupled to a respective hardware task scheduler, each channel is coupled to a respective channel task scheduler, and each external node is coupled to a proxy task scheduler. The task schedulers communicate via pending and decrement signals with a hardware scheduler crossbar. With this arrangement, the HTS couples a first subset of task schedulers in a first data processing order with the associated data processing nodes performing the tasks, and couples a second subset of task schedulers in a second data processing order with the associated data processing nodes performing the tasks.

公开(公告)号：US12100063B2

公开(公告)日：2024-09-24

申请号：US17879251

申请日：2022-08-02

Applicant: Texas Instruments Incorporated

Inventor： Hrushikesh Tukaram Garud ,  Ankit Ajmani ,  Soyeb Noormohammed Nagori ,  Mihir Narendra Mody

IPC: H04N19/91 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  H04N19/91 ,  G06T2200/28

Abstract: A computer vision system is provided that includes a camera capture component configured to capture an image from a camera, a memory, and an image compression decompression engine (ICDE) coupled to the memory and configured to receive each line of the image, and compress each line to generate a compressed bit stream. To compress a line, the ICDE is configured to divide the line into compression units, and compress each compression unit, wherein to compress a compression unit, the ICDE is configured to perform delta prediction on the compression unit to generate a delta predicted compression unit, compress the delta predicted compression unit using exponential Golomb coding to generate a compressed delta predicted compression unit, and add the compressed delta predicted compression unit to the compressed bit stream.

公开(公告)号：US12093697B2

公开(公告)日：2024-09-17

申请号：US17721534

申请日：2022-04-15

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  G06F12/14 ,  G06F21/57 ,  G06F21/78 ,  H04L9/32

CPC classification number: G06F9/4401 ,  G06F12/14 ,  G06F12/1416 ,  G06F12/1483 ,  G06F21/57 ,  H04L9/3247 ,  G06F21/78

Abstract: An example apparatus includes: a first interface configured to couple to a processor core; a second interface configured to couple to a first memory configured to store an image that includes a set of slices; a third interface coupled to the first interface, the third interface configured to couple to a second memory; a direct memory access circuit coupled to the second interface and the third interface and configured to: receive a transaction from the second interface, wherein the transaction specifies a read of a slice of the set of slices; and based on the transaction: read the slice from the first memory; perform on-the-fly operations to the slice; and store the slice in the second memory.

公开(公告)号：US12013931B2

公开(公告)日：2024-06-18

申请号：US17550948

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish Chitnis ,  Mihir Narendra Mody ,  Amritpal Singh Mundra ,  Yashwant Dutt ,  Gregory Raymond Shurtz ,  Robert John Tivy

IPC: G06F21/54 ,  G06F9/48 ,  G06F21/55 ,  G06F21/79

CPC classification number: G06F21/54 ,  G06F9/485 ,  G06F21/554 ,  G06F21/79

Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.

公开(公告)号：US12010330B2

公开(公告)日：2024-06-11

申请号：US18123432

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20240176488A1

公开(公告)日：2024-05-30

申请号：US18060457

申请日：2022-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Mel Alan Phipps ,  Prasad Jondhale ,  Mohd Asif Farooqui ,  Shailesh Ghotgalkar

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.

公开(公告)号：US11995472B2

公开(公告)日：2024-05-28

申请号：US17378841

申请日：2021-07-19

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Kedar Satish Chitnis ,  Kumar Desappan ,  David Smith ,  Pramod Kumar Swami ,  Shyam Jagannathan

IPC: G06F9/50 ,  G06F9/455 ,  G06F12/00 ,  G06F12/02 ,  G06N3/02 ,  G06N3/10 ,  G06N20/00

CPC classification number: G06F9/5016 ,  G06F9/5077 ,  G06F12/00 ,  G06F12/0223 ,  G06F2009/45583 ,  G06F9/50 ,  G06F9/5022 ,  G06N3/02 ,  G06N3/10 ,  G06N20/00

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.