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公开(公告)号：US11640357B2
公开(公告)日：2023-05-02
申请号：US16882231
申请日：2020-05-22
Applicant: Texas Instruments Incorporated
Inventor： Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
IPC: G06F12/08 , G06F12/00 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
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192.发明授权公开(公告)号：US11636040B2
公开(公告)日：2023-04-25
申请号：US16882252
申请日：2020-05-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
IPC: G06F12/00 , G06F13/00 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.
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公开(公告)号：US11609862B2
公开(公告)日：2023-03-21
申请号：US17665958
申请日：2022-02-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Timothy David Anderson , Mujibur Rahman
IPC: G06F9/30 , G06F12/1045 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F15/78
Abstract: A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.
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公开(公告)号：US11500631B2
公开(公告)日：2022-11-15
申请号：US16878610
申请日：2020-05-20
Applicant: Texas Instruments Incorporated
Inventor： Mujibur Rahman , Timothy David Anderson
Abstract: A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.
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公开(公告)号：US11449336B2
公开(公告)日：2022-09-20
申请号：US16786457
申请日：2020-02-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.
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Patent Agency Ranking
公开(公告)号：US11422938B2
公开(公告)日：2022-08-23
申请号：US16653139
申请日：2019-10-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Matthew David Pierson , Kai Chirca , Timothy David Anderson
IPC: G06F12/084 , G06F12/0831 , G06F9/48 , G06F9/50 , G06F12/0891 , G06F12/0811 , G06F12/1009 , G06F12/0875 , G06F12/10 , G06F13/16 , G06F13/40 , G06F12/0855 , G06F12/06 , G06F12/0817 , G06F13/12 , G06F3/06 , G06F12/0815 , H03M13/01 , H03M13/09 , H03M13/15 , H03M13/27 , G06F9/30 , G06F9/38 , G06F12/0846 , G06F12/0862
Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.
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公开(公告)号：US20220244957A1
公开(公告)日：2022-08-04
申请号：US17720657
申请日：2022-04-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Joseph Raymond Michael Zbiciak , Timothy David Anderson , Jonathan (Son) Hung Tran , Kai Chirca , Daniel Wu , Abhijeet Ashok Chachad , David M. Thompson
IPC: G06F9/30 , G06F9/345 , G06F12/0875 , G06F9/38 , G06F9/32 , G06F12/0897 , G06F11/10 , G06F11/00 , G06F12/0862 , G06F12/1036
Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.
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公开(公告)号：US11347503B2
公开(公告)日：2022-05-31
申请号：US16878607
申请日：2020-05-20
Applicant: Texas Instruments Incorporated
Inventor： Asheesh Bhardwaj , Mujibur Rahman , Timothy David Anderson
IPC: G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
Abstract: A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.
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公开(公告)号：US20220156192A1
公开(公告)日：2022-05-19
申请号：US17589648
申请日：2022-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kai Chirca , Matthew David Pierson , David E. Smith , Timothy David Anderson
IPC: G06F12/084 , G06F12/0811 , G06F12/1009 , G06F12/0875 , G06F12/10 , G06F13/16 , G06F13/40 , G06F12/0855 , G06F12/06 , G06F12/0817 , G06F12/0831 , G06F13/12 , G06F3/06 , G06F12/0815 , H03M13/01 , H03M13/09 , H03M13/15 , H03M13/27 , G06F9/30 , G06F9/38 , G06F9/48 , G06F9/50 , G06F12/0891
Abstract: Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.
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公开(公告)号：US11294673B2
公开(公告)日：2022-04-05
申请号：US16878608
申请日：2020-05-20
Applicant: Texas Instruments Incorporated
Inventor： Timothy David Anderson , Mujibur Rahman
IPC: G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
Abstract: A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.
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