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公开(公告)号：US20220078052A1
公开(公告)日：2022-03-10
申请号：US17482659
申请日：2021-09-23
Applicant: Rambus Inc.
Inventor： Ramin Farjad-Rad
IPC: H04L25/03
Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.
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192.发明申请公开(公告)号：US20220070032A1
公开(公告)日：2022-03-03
申请号：US17400945
申请日：2021-08-12
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03 , H01J37/00 , H01L21/311 , H01L21/67 , H01L21/683 , H01L21/768 , H01L29/66
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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公开(公告)号：US11258641B2
公开(公告)日：2022-02-22
申请号：US17181883
申请日：2021-02-22
Applicant: Rambus Inc.
Inventor： Nanyan Wang , Vadim Moshinsky , Prashant Choudhary
Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.
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公开(公告)号：US11258522B2
公开(公告)日：2022-02-22
申请号：US17024835
申请日：2020-09-18
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号：US11239855B2
公开(公告)日：2022-02-01
申请号：US17166919
申请日：2021-02-03
Applicant: Rambus Inc.
Inventor： Shankar Tangirala
Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.
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Patent Agency Ranking
公开(公告)号：US11238003B2
公开(公告)日：2022-02-01
申请号：US16734839
申请日：2020-01-06
Applicant: Rambus Inc.
Inventor： Yuanlong Wang
IPC: G06F1/00 , G06F13/42 , G06F1/3237 , G06F1/3206 , G06F1/3234
Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
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公开(公告)号：US20220027093A1
公开(公告)日：2022-01-27
申请号：US17428105
申请日：2020-02-05
Applicant: Rambus Inc.
Inventor： Frederick A. Ware
Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit- serial data signals over M of the N external signaling links, where M is less than N.
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公开(公告)号：US20220005542A1
公开(公告)日：2022-01-06
申请号：US17368018
申请日：2021-07-06
Applicant: Rambus Inc.
Inventor： Scott C. Best , John Eric Linstadt , Paul William Roukema
Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
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公开(公告)号：US20220004472A9
公开(公告)日：2022-01-06
申请号：US16670798
申请日：2019-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C29/52 , G11C11/4093
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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公开(公告)号：US11211139B2
公开(公告)日：2021-12-28
申请号：US16824005
申请日：2020-03-19
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Wayne F. Ellis , Akash Bansal
IPC: G11C5/04 , G11C29/50 , G06F13/16 , G01R23/02 , G11C7/22 , G11C29/02 , H03L1/02 , G11C8/18 , G06F11/16 , G06F1/12 , G06F1/08 , G01R23/15 , G01R35/00 , G11C7/04
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
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