公开(公告)号：US5946237A

公开(公告)日：1999-08-31

申请号：US826489

申请日：1997-03-27

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C5/02 ,  G11C16/28 ,  G11C16/06

CPC classification number: G11C5/025 ,  G11C16/28

Abstract: A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing component that are adapted to receive the data of the memory matrix for reading, which has the particularity that the memory matrix is divided into at least two half-matrices. Each one of the two half-matrices has a reference line that is adapted to constitute a reference for reading the other half-matrix. The data sensing component receives the data from one half-matrix and the reference from the other half-matrix and is adapted to transmit, according to a control timing, the data on an internal bus.

Abstract translation: 用于存储器件，特别是非易失性类型的存储器件的数据读取路径管理架构包括适于接收用于读取的存储器矩阵的数据的存储器矩阵和数据感测部件，其特征在于存储器矩阵是 分为至少两个半矩阵。 两个半矩阵中的每一个具有适于构成用于读取另一半矩阵的参考的参考线。 数据感测组件从一个半矩阵和另一个半矩阵的参考接收数据，并且适于根据控制定时在内部总线上发送数据。

公开(公告)号：US5945819A

公开(公告)日：1999-08-31

申请号：US865393

申请日：1997-05-29

Applicant: Riccardo Ursino ,  Roberto Gariboldi

Inventor： Riccardo Ursino ,  Roberto Gariboldi

IPC: G05F1/575 ,  G05F1/40

CPC classification number: G05F1/575

Abstract: The invention relates to a voltage regulator connected between first and second voltage references and having an output terminal for delivering a regulated output voltage. The voltage regulator includes at least one voltage divider, connected between the output terminal and the second voltage reference, and a serial output element connected between the output terminal and the first voltage reference. The voltage divider is connected to the serial output element by a first conduction path which includes at least one error amplifier whose output is connected to at least one driver for turning off the serial output element. The voltage regulator includes, between the voltage divider and the serial output element, at least a second conduction path for turning off the serial output element according to a value of the regulated output voltage in advance of the action of the first conduction path.

Abstract translation: 本发明涉及连接在第一和第二参考电压之间的电压调节器，并且具有用于传送稳定的输出电压的输出端子。 电压调节器包括连接在输出端和第二参考电压之间的至少一个分压器，以及连接在输出端和第一参考电压之间的串联输出元件。 分压器通过第一导电路径连接到串行输出元件，第一导电路径包括至少一个误差放大器，其输出端连接至至少一个用于关断串行输出元件的驱动器。 电压调节器在分压器和串行输出元件之间包括至少第二导电路径，用于在第一导电路径的作用之前根据调节的输出电压的值来关断串行输出元件。

公开(公告)号：US5936907A

公开(公告)日：1999-08-10

申请号：US183469

申请日：1998-10-30

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C29/00 ,  G11C29/44 ,  G11C13/06

CPC classification number: G11C29/835 ,  G11C29/44

Abstract: A method for detecting redunded defective addresses in a memory device with redundancy including at least one memory register for storing at least one defective address. The memory register includes a plurality of memory units each one storing a defective address bit and comparing the defective address bit with a respective current address bit supplied to the memory device; the memory register activates a respective redundancy selection signal when the current address coincides with the defective address stored therein. The method provides for: activating a forcing signal for forcing the activation of the redundancy selection signal to be independent of the coincidence of a first group of current address bits, associated to a respective first group of the memory units, with the defective address bits stored in the respective first group of memory units; scanning all the possible configurations of a second group of current address bits associated with a second group of the memory units and sequentially supplying the memory device with all the configurations; detecting a configuration of the second group of current address bits for which the redundancy selection signal is activated; while supplying the memory device with the configuration of the second group of current address bits, deactivating the forcing signal and sequentially supplying the memory device with a scanning of all the possible configurations of the first group of address bits; detecting a configuration of the first group of current address bits for which the redundancy selection signal is activated.

Abstract translation: 一种用于检测具有冗余的存储器件中的冗余缺陷地址的方法，包括用于存储至少一个缺陷地址的至少一个存储器寄存器。 存储器寄存器包括多个存储器单元，每个存储器单元存储缺陷地址位，并将缺陷地址位与提供给存储器件的相应当前地址位进行比较; 当当前地址与其中存储的缺陷地址一致时，存储器寄存器激活相应的冗余选择信号。 该方法提供：激活强制信号以迫使冗余选择信号的激活独立于与相应的第一组存储器单元相关联的当前地址位的第一组的一致性，存储有缺陷的地址位 在相应的第一组存储器单元中; 扫描与第二组存储器单元相关联的第二组当前地址位的所有可能配置，并且向存储器设备顺序地提供所有配置; 检测所述冗余选择信号被激活的第二组当前地址位的配置; 同时向存储器件提供第二组当前地址位的配置，去激活强制信号并且顺序地向存储器件提供对第一组地址位的所有可能配置的扫描; 检测冗余选择信号被激活的第一组当前地址位的配置。

公开(公告)号：US5936284A

公开(公告)日：1999-08-10

申请号：US963192

申请日：1997-11-03

Applicant: Enrico M. A. Ravanelli

Inventor： Enrico M. A. Ravanelli

IPC: H01L27/02 ,  H01L29/732 ,  H01L23/62 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70

CPC classification number: H01L29/7322 ,  H01L27/0248 ,  H01L27/0259

Abstract: A circuit protects against electrostatic discharge and includes a transistor connected to the circuit to be protected. A semiconductor body of a first conductivity type serves as the collector. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter. The first doped region includes a generally H-shaped doped region and a generally ring-shaped doped region forming an opening in which the second doped region serving as the emitter is received. The H-shaped doped region has a deeper junction surface than the junction surface of the ring-shaped doped region, and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region. The H-shaped doped region achieves a low collector-to-base breakdown voltage and the ring-shaped doped region achieves a low snap-back voltage. A method for forming the transistor is also disclosed.

Abstract translation: 电路可防止静电放电，并包括连接到待保护电路的晶体管。 第一导电类型的半导体本体用作集电极。 第二导电类型的第一掺杂区域包含在半导体本体中并用作基底。 第一导电类型的第二掺杂区域包含在第一掺杂区域中并且用作发射极。 第一掺杂区域包括大致H形掺杂区域和形成开口的大致环形掺杂区域，其中接收用作发射极的第二掺杂区域。 H形掺杂区域具有比环形掺杂区域的结表面更深的结表面，以及小于环形掺杂区域的掺杂剂浓度的掺杂剂浓度。 H形掺杂区域实现了低集电极到基极击穿电压，并且环形掺杂区域实现了低的反冲电压。 还公开了一种用于形成晶体管的方法。

公开(公告)号：US5929918A

公开(公告)日：1999-07-27

申请号：US801950

申请日：1997-02-12

Applicant: Ricardo Alberto Marques Pereira ,  Massimo Mancuso ,  Rinaldo Poluzzi

Inventor： Ricardo Alberto Marques Pereira ,  Massimo Mancuso ,  Rinaldo Poluzzi

IPC: H04N5/208 ,  G06T5/20 ,  G06T7/60 ,  H03H17/00 ,  H04N5/44 ,  H04N7/01

CPC classification number: H04N7/012 ,  H04N7/0132

Abstract: An interpolation filter for video signals includes four circuits to improve video quality in both intra-field and inter-field modes. The interpolation filter is configured to interpolate according to the direction of an image edge. The interpolation filter is also configured to interpolate in a prescribed spatial direction when no image edges can be univocally determined. The first circuit detects an image edge of discrete image elements to generate a first signal. The second circuit uses output from the first circuit to generate a first signal corresponding to an average of the discrete image elements along a direction of the image edge. The third circuit uses output from the first circuit to detect a texture image area wherein an image edge cannot be univocally determined and for generating a second signal depending on a degree of existence of the image edge. The fourth circuit is supplied by the first signal, the second signal and a third signal. The fourth circuit generates an output signal obtained by combining the first signal with the third signal in a proportion dependent upon the second signal. Additionally, the fourth circuit is configured for multiplexing to selectively couple the third signal to a fourth signal, corresponding to an average of the discrete image elements along a prescribed direction, or to a fifth signal corresponding to a previously received image element value.

Abstract translation: 用于视频信号的内插滤波器包括四个电路，以改善场内和场外模式中的视频质量。 内插滤波器被配置为根据图像边缘的方向进行插值。 内插滤波器也被配置为当不能确定图像边缘时，在规定的空间方向内插。 第一电路检测离散图像元素的图像边缘以产生第一信号。 第二电路使用来自第一电路的输出来产生对应于沿着图像边缘的方向的离散图像元素的平均值的第一信号。 第三电路使用来自第一电路的输出来检测纹理图像区域，其中图像边缘不能被单一地确定，并且用于根据图像边缘的存在程度产生第二信号。 第四电路由第一信号，第二信号和第三信号提供。 第四电路产生通过将第一信号与第三信号以取决于第二信号的比例组合而获得的输出信号。 此外，第四电路被配置为用于多路复用以选择性地将第三信号耦合到对应于沿着规定方向的离散图像元素的平均值的第四信号，或者对应于先前接收到的图像元素值的第五信号。

公开(公告)号：US5905677A

公开(公告)日：1999-05-18

申请号：US831046

申请日：1997-04-01

Applicant: Giulio Casagrande ,  Emilio Camerlenghi

Inventor： Giulio Casagrande ,  Emilio Camerlenghi

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

Abstract translation: 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。

公开(公告)号：US5896057A

公开(公告)日：1999-04-20

申请号：US865721

申请日：1997-05-30

Applicant: Stefania Chicca ,  Vanni Poletto ,  Marco Morelli

Inventor： Stefania Chicca ,  Vanni Poletto ,  Marco Morelli

IPC: G01R31/00 ,  H02H7/08 ,  H02H7/122 ,  H03K17/56

CPC classification number: H02H7/0844 ,  G01R31/006 ,  H02H7/1225

Abstract: A troubleshooting circuit for locating malfunctions while driving an electric load by means of a bridge stage (M1, M2, M3, M4) which is connected between ground (GND) and the power supply (+VCC) in series with first and second resistors (Rsl, Rsh), respectively. First (COMP1) and second (COMP2) threshold comparators are coupled to the first resistor to sense a short-circuit to battery (+VCC) and an open-load condition, respectively. Coupled to the second resistor is a third threshold comparator (COMP3) adapted to sense a short-circuit to ground. The output signals from the comparators are sampled through flip-flops (FF1, FF2, FF3, FF4, FF5, FF6) upon a transistor in the bridge being switched to the off state.

Abstract translation: 用于通过连接在接地（GND）和与第一和第二电阻器（GND）和电源（+ VCC）串联的桥接级（M1，M2，M3，M4）来驱动电力负载的定位故障的故障排除电路 Rsl，Rsh）。 第一（COMP1）和第二（COMP2）阈值比较器分别耦合到第一电阻器以感测到电池（+ VCC）和开路负载条件的短路。 耦合到第二电阻器的是第三阈值比较器（COMP3），其适于感测到对地短路。 当桥接器中的晶体管切换到关闭状态时，来自比较器的输出信号通过触发器（FF1，FF2，FF3，FF4，FF5，FF6）进行采样。

公开(公告)号：US5889710A

公开(公告)日：1999-03-30

申请号：US842835

申请日：1997-04-17

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/84

Abstract: A semiconductor memory device includes: a matrix of memory cells including a plurality of rows of memory cells; first means for generating a first internal timing signal activated upon changing of a current address supplied to the memory device, the first timing signal remaining activated for a prescribed time substantially at the beginning of a read cycle of the memory device; row address decoding means supplied by the current address for selecting a row of memory cells; second means for storing defective addresses of defective rows in the matrix of memory cells, for comparing the defective addresses with a current address supplied to the memory device, for selecting a redundancy row when the current address coincides with one of the defective addresses and for correspondingly deactivating the row address decoding means to prevent the selection of the defective row. The memory device includes redundancy control means supplied by the first timing signal, the redundancy control means enabling said row address decoder means at the beginning of the read cycle independently of the current address and maintains the row address decoder means enabled until the first timing signal is deactivated.

Abstract translation: 半导体存储器件包括：包括多行存储器单元的存储器单元矩阵; 第一装置，用于产生在改变提供给存储器件的当前地址时激活的第一内部定时信号，第一定时信号基本上在存储器件的读取周期开始时保持激活规定时间; 行地址解码装置，由当前地址提供，用于选择一行存储器单元; 用于将缺陷地址存储在存储器单元矩阵中，用于将缺陷地址与提供给存储器件的当前地址进行比较，用于当当前地址与缺陷地址之一一致时选择冗余行; 停止行地址解码装置以防止对缺陷行的选择。 存储装置包括由第一定时信号提供的冗余控制装置，冗余控制装置使能所述行地址解码装置在读周期开始时独立于当前地址，并维持行地址解码装置使能直到第一定时信号为 停用

公开(公告)号：US5888836A

公开(公告)日：1999-03-30

申请号：US990328

申请日：1997-12-15

Applicant: Emilio Ghio ,  Simone Alba ,  Andrea Colognese

Inventor： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/268

CPC classification number: H01L29/66825 ,  H01L21/28176

Abstract: The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

Abstract translation: 所描述的方法需要形成与已知方法制造的那些结构完全相似的浮栅非易失性存储单元。 该方法包括在较低温度（430℃）下进行退火处理，以修复等离子体处理造成的损坏。 为了获得接近理论值的电池的阈值电压值，特别是对于具有特别延长的互连的电池，在退火处理之前对电池进行紫外线辐射，以便中和存在于浮栅电极中的任何电荷 细胞。

公开(公告)号：US5886945A

公开(公告)日：1999-03-23

申请号：US825138

申请日：1997-03-28

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C16/32

Abstract: The circuit includes a memory element connected to an enabling input receiving an enabling signal, and in turn including a first reset circuit receiving an internal reset signal, and a second reset circuit receiving an external timing control signal, to generate an operating step enabling signal having a first switching edge on receiving the enabling signal, a second switching edge on receiving the reset signal, and a third switching edge on receiving the external timing control signal. A control input receives a timing mode signal, and is connected to the first and second reset circuits to enable them selectively. By enabling the second reset circuit and supplying the external timing control signal, in successive cycles, with different delays in relation to the enabling signal, different readings of the memory are enabled to characterize the response and optimize the timing of the memory device.

Abstract translation: 电路包括连接到使能输入的存储器元件，其接收使能信号，并且进而包括接收内部复位信号的第一复位电路和接收外部定时控制信号的第二复位电路，以产生具有 接收使能信号的第一开关沿，接收复位信号的第二开关沿，以及接收外部定时控制信号时的第三开关沿。 控制输入​​接收定时模式信号，并连接到第一和第二复位电路以使其能够选择。 通过启用第二复位电路并且在连续周期中提供外部定时控制信号，具有与使能信号相关的不同延迟，能够使存储器的不同读数表征响应并优化存储器件的定时。