公开(公告)号：US5867066A

公开(公告)日：1999-02-02

申请号：US631733

申请日：1996-04-11

Applicant: Francis Dell'Ova ,  Bruno Bonhoure ,  Frederic Paillardet

Inventor： Francis Dell'Ova ,  Bruno Bonhoure ,  Frederic Paillardet

IPC: H03F1/56 ,  G05F3/26 ,  G11B7/00 ,  H03F3/08 ,  H03F3/34 ,  H03F3/345 ,  H03F3/347

CPC classification number: G11B7/005 ,  H03F3/08 ,  H03F3/082 ,  H03F3/345 ,  G11B7/13

Abstract: A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.

公开(公告)号：US5864503A

公开(公告)日：1999-01-26

申请号：US866531

申请日：1997-05-30

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/34 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/3454

Abstract: A method for verifying an electrically programmable non-volatile memory cell of an electrically programmable memory device after programming, providing for accessing the memory cell after having submitted the same to at least a programming pulse by means of a sensing circuit, checking an output of the sensing circuit, and submitting said memory cell to further programming pulses if said output of the sensing circuit corresponds to a non-programmed memory cell. The checking an output of the sensing circuit is performed at a first instant of time which is anticipated of a prescribed time interval with respect to a second instant of time at which said output of the sensing circuit is checked in a normal read operation of the memory device, said prescribed time interval corresponding to a prescribed security margin of programming of the memory cell. (FIGS. 2 and 4).

Abstract translation: 一种用于在编程之后验证电可编程存储器件的电可编程非易失性存储单元的方法，用于在通过感测电路将其提交到至少编程脉冲之后提供访问存储器单元， 并且如果感测电路的所述输出对应于非编程存储器单元，则将所述存储单元提交以进一步编程脉冲。 检测感测电路的输出是在第一时刻进行的，该第一时刻是相对于在存储器的正常读取操作中检查感测电路的所述输出的第二时刻的预定时间间隔 设备，所述规定的时间间隔对应于存储器单元的规定的编程安全余量。 （图2和图4）。

公开(公告)号：US5859797A

公开(公告)日：1999-01-12

申请号：US846753

申请日：1997-04-30

Applicant: Marco Maccarrone ,  Jacopo Mulatti ,  Carla Maria Golla

Inventor： Marco Maccarrone ,  Jacopo Mulatti ,  Carla Maria Golla

IPC: G11C16/30 ,  G11C7/00

CPC classification number: G11C16/30

Abstract: A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.

Abstract translation: 一种用于在读入包括EPROM或闪存类型的至少一个存储元件并具有要偏置的控制端子和导电端子的冗余UPROM单元的电路中产生偏置信号的电路，以及连接存储元件与参考电压的MOS晶体管 低电源电压包括用于产生要施加到存储元件的控制端的第一电压输出信号的电压升压器和连接到升压器的输出的电压信号的限制网络。 还提供了用于产生要施加到上述晶体管之一的控制端子的第二电压输出信号的电路部分。 该电路部分包括与产生第二电压信号的部分的升压器互锁的定时部分。

公开(公告)号：US5855693A

公开(公告)日：1999-01-05

申请号：US571806

申请日：1995-12-13

Applicant: Bruno Murari ,  Flavio Villa ,  Ubaldo Mastromatteo

Inventor： Bruno Murari ,  Flavio Villa ,  Ubaldo Mastromatteo

IPC: H01L21/02 ,  H01L21/20 ,  H01L27/00 ,  H01L27/12 ,  H01L21/265

CPC classification number: H01L21/2007 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01074 ,  H01L2924/14

Abstract: A wafer of semiconductor material for fabricating integrated devices, including a stack of superimposed layers including first and second monocrystalline silicon layers separated by an intermediate insulating layer made of a material selected from the group comprising silicon carbide, silicon nitride and ceramic materials. An oxide bond layer is provided between the intermediate layer and the second silicon layer. The wafer is fabricated by forming the intermediate insulating layer on the first silicon layer in a heated vacuum chamber; depositing the oxide layer; and superimposing the second silicon layer. When the stack of silicon, insulating material, oxide and silicon layers is heat treated, the oxide reacts so as to bond the insulating layer to the second silicon layer. As a ceramic material beryllium oxide, aluminium nitride, boron nitride and alumina may be used.

Abstract translation: 一种用于制造集成器件的半导体材料晶片，包括由包括由碳化硅，氮化硅和陶瓷材料组成的材料制成的中间绝缘层分隔的第一和第二单晶硅层的叠加层。 在中间层和第二硅层之间设置氧化物接合层。 通过在加热的真空室中在第一硅层上形成中间绝缘层来制造晶片; 沉积氧化层; 并叠加第二硅层。 当硅，绝缘材料，氧化物和硅层的堆叠被热处理时，氧化物反应以将绝缘层粘合到第二硅层。 作为陶瓷材料氧化铍，可以使用氮化铝，氮化硼和氧化铝。

公开(公告)号：US5854762A

公开(公告)日：1998-12-29

申请号：US961368

申请日：1997-10-30

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/22 ,  G11C29/00 ,  G11C16/06

CPC classification number: G11C29/78 ,  G11C16/225

Abstract: A protection circuit for electrically programmable non-volatile memory cells includes at least one first control circuit connected between first and second voltage references and having at least an input terminal and an output terminal wherein the output terminal delivers a reading/programming voltage signal to the cells. The protection circuit also includes at least one second control circuit having a first input terminal for receiving an enabling control signal, a second input terminal for receiving a Power-on-Reset signal, and an output terminal for supplying a control signal to the first input terminal of the first control circuit. The protection circuit further includes a disabling circuit connected between the first and the second voltage reference and having an output terminal connected to the first input terminal of the first control circuit. The disabling circuit comprises at least one redundant memory element connected between a translated voltage reference and the second voltage reference.

Abstract translation: 用于电可编程非易失性存储单元的保护电路包括连接在第一和第二电压基准之间的至少一个第一控制电路，并且至少具有一个输入端子和一个输出端子，其中输出端子将一个读取/编程电压信号传送到该单元 。 保护电路还包括至少一个第二控制电路，其具有用于接收使能控制信号的第一输入端子，用于接收上电复位信号的第二输入端子和用于向第一输入端提供控制信号的输出端子 端子的第一控制电路。 保护电路还包括连接在第一和第二参考电压之间并具有连接到第一控制电路的第一输入端的输出端的禁用电路。 禁用电路包括连接在转换的电压基准和第二电压基准之间的至少一个冗余存储元件。

公开(公告)号：US5854481A

公开(公告)日：1998-12-29

申请号：US688830

申请日：1996-07-31

Applicant: Giulio Ricotti ,  Roberto Bardelli ,  Domenico Rossi

Inventor： Giulio Ricotti ,  Roberto Bardelli ,  Domenico Rossi

IPC: H03K17/687 ,  G06K19/06

CPC classification number: H03K17/6874

Abstract: A circuit for modifying a resonant frequency of a receiver for radio frequency signals. The receiver includes an inductor connected in parallel with a capacitor. The circuit includes a switch having an additional capacitor connected between two MOS transistors, the switch being connected in parallel with the receiver to add capacitance based on a control of the MOS transistors.

Abstract translation: 一种用于修改射频信号的接收机的谐振频率的电路。 接收器包括与电容器并联连接的电感器。 电路包括具有连接在两个MOS晶体管之间的附加电容器的开关，该开关与接收器并联连接，以便基于MOS晶体管的控制来增加电容。

公开(公告)号：US5847504A

公开(公告)日：1998-12-08

申请号：US690895

申请日：1996-08-01

Applicant: Livio Baldi

Inventor： Livio Baldi

IPC: G09G3/22 ,  H01J1/304 ,  H01J31/12 ,  H01J1/62 ,  H01J1/02 ,  H01J1/16 ,  H01J63/04

CPC classification number: G09G3/22 ,  H01J1/3042 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00

Abstract: A pixel emission current limiting resistance is realized by forming a stack of alternately doped amorphous or polycrystalline silicon layers over the cathodic conductors of a FED driving matrix. The stack of amorphous or polycrystalline silicon layers doped alternately n and p provides at least a reversely biased n/p junction having a leakage current that matches the required level of pixel emission current. The reversely biased junction constitutes a nonlinear series resistance that is quite effective in limiting the emission current through any one of the microtips that form an individually excitable pixel and which are formed on the uppermost layer of the stack.

Abstract translation: 通过在FED驱动矩阵的阴极导体上形成交替掺杂的非晶或多晶硅层的堆叠来实现像素发射电流限制电阻。 掺杂交替地n和p的非晶或多晶硅层的堆叠提供至少一个具有与所要求的像素发射电流水平匹配的漏电流的反向偏置n / p结。 反向偏置的结构成非线性串联电阻，其非常有效地限制通过形成可单独激发的像素并且形成在堆叠的最上层上的任何一个微尖端的发射电流。

公开(公告)号：US5838597A

公开(公告)日：1998-11-17

申请号：US758805

申请日：1996-12-03

Applicant: Danilo Pau ,  Roberto Sannino

Inventor： Danilo Pau ,  Roberto Sannino

IPC: H04N5/455 ,  G06T9/00 ,  H03M7/38 ,  H04N7/26 ,  H04N7/30 ,  H04N7/34 ,  H04N7/50 ,  G06F17/00

CPC classification number: H04N19/428 ,  H04N19/42 ,  H04N19/423 ,  H04N19/593 ,  H04N19/61

Abstract: The video RAM requisite of an MPEG-2 decoder is reduced by recompressing according to an adaptive pulse code modulation scheme (ADPCM) at least the I and P pictures, after MPEG-2 decompression and before storing the relative data in the video RAM. The ADPCM recompressed and coded data written in the video RAM are decoded and decompressed during the reconstruction of a B-picture to be displayed.

Abstract translation: 至少在MPEG-2解压缩之后并且将相对数据存储在视频RAM中之前，根据至少I图像和P图像的自适应脉码调制方案（ADPCM）对MPEG-2解码器的视频RAM要求进行减小。 写入到视频RAM中的ADPCM再压缩和编码数据在重建待显示的B图像期间被解码和解压缩。

公开(公告)号：US5834976A

公开(公告)日：1998-11-10

申请号：US756024

申请日：1996-11-26

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

IPC: H03F1/08 ,  H03F1/14 ,  H03F1/34

CPC classification number: H03F1/086

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage and an amplifier output stage connected serially together to receive an input signal on at least one input terminal of the amplifier and generate an amplified signal on an output terminal of the amplifier. Provided between the input and output stages is an intermediate node which is connected to a compensation block to receive a frequency-variable compensation signal therefrom. The compensation block is coupled with its input to the input terminal of the amplifier The compensation block is connected to receive at least the feedback signal. Preferably, the compensation signal is variable as a function of a gain value which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value.

Abstract translation: 相对于闭环增益自补偿的运算放大器频率包括跨导输入级和串联连接的放大器输出级，以在放大器的至少一个输入端上接收输入信号，并在输出端产生放大信号 的放大器。 在输入级和输出级之间设置有中间节点，其连接到补偿块以从其接收频率可变的补偿信号。 补偿块与其输入耦合到放大器的输入端子。补偿块被连接以至少接收反馈信号。 优选地，补偿信号作为由反馈电路确定的增益值的函数而变化，并且补偿信号的所述变化以与增益值成反比关系的关系发生。

公开(公告)号：US5831466A

公开(公告)日：1998-11-03

申请号：US777182

申请日：1996-12-27

Applicant: Francesco Pulvirenti ,  Gregorio Bontempo ,  Roberto Gariboldi

Inventor： Francesco Pulvirenti ,  Gregorio Bontempo ,  Roberto Gariboldi

IPC: H03K17/08 ,  H03K17/082 ,  H02H1/00

CPC classification number: H03K17/0822 ,  H03K2017/0806 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator. The method of this invention provides for: the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; and the utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function. The power transistor (PW) is turned on again, and the current limiting circuit (4) inhibited, by the following steps: a) generating an electric signal which is substantially proportional to the voltage appearing at the output terminal (OUT) of the actuator; b) driving the control terminal (G) of the power transistor (PW) by means of said electric signal, and causing said transistor to conduct, while simultaneously disabling the current limiting circuit (4) when the output voltage exceeds a predetermined threshold; and c) allowing the transient energy to be dissipated to the power transistor (PW).

Abstract translation: 本发明的目的在于提供一种用于保护功率执行器的输出级的方法和电路，以防止浪涌型的电压瞬变。 特别地，它提供了针对包含在执行器的输出级中的功率晶体管的国际标准IEC 801-5所述类型的电压浪涌瞬变的保护。 本发明的方法提供：功率晶体管（PW）本征二极管（DP）用于在正瞬变期间将瞬态能量倾倒到一个供电发生器端子; 以及在负瞬态期间将功率晶体管（PW）恢复特性应用于导通状态以将能量倾倒在其中，同时抑制电流限制功能。 功率晶体管（PW）再次导通，并且限流电路（4）通过以下步骤来禁止：a）产生与执行器的输出端（OUT）出现的电压基本成正比的电信号 ; b）通过所述电信号驱动功率晶体管（PW）的控制端（G），并使所述晶体管导通，同时在所述输出电压超过预定阈值时使所述限流电路（4）同时禁用; 和c）允许瞬态能量被耗散到功率晶体管（PW）。