公开(公告)号：US20220291446A1

公开(公告)日：2022-09-15

申请号：US17197133

申请日：2021-03-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Qizhi Liu

IPC: G02B6/124 ,  G02B6/13

Abstract: Embodiments of the disclosure provide an optical antenna for a photonic integrated circuit (PIC). The optical antenna includes a semiconductor waveguide on a semiconductor layer. The semiconductor waveguide includes a first vertical sidewall over the semiconductor layer over the semiconductor layer. A plurality of grating protrusions extends horizontally from the first vertical sidewall of the semiconductor waveguide.

公开(公告)号：US20220285523A1

公开(公告)日：2022-09-08

申请号：US17191886

申请日：2021-03-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.

公开(公告)号：US11437568B2

公开(公告)日：2022-09-06

申请号：US16836434

申请日：2020-03-31

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.

公开(公告)号：US11437286B2

公开(公告)日：2022-09-06

申请号：US17012266

申请日：2020-09-04

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

公开(公告)号：US11437080B2

公开(公告)日：2022-09-06

申请号：US17092384

申请日：2020-11-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Xiaoxiao Li ,  Lei Zhang

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.

公开(公告)号：US11430881B2

公开(公告)日：2022-08-30

申请号：US16810076

申请日：2020-03-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anindya Nath ,  Alain F. Loiseau

IPC: H01L29/04 ,  H01L29/74 ,  H01L29/73

Abstract: The present disclosure relates to a polysilicon-diode triggered compact silicon controlled rectifier. In particular, the present disclosure relates to a structure including a silicon controlled rectifier (SCR) which includes an n-well adjacent and in direct contact with a p-well, the SCR includes at least one shallow trench isolation (STI) region, and at least one polysilicon diode on top of the at least one STI region.

公开(公告)号：US11424377B2

公开(公告)日：2022-08-23

申请号：US17065862

申请日：2020-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Ramsey Hazbun

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US11422305B2

公开(公告)日：2022-08-23

申请号：US17109559

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yangyang Liu ,  Tymon Barwicz

IPC: G02B6/125 ,  G02B6/13 ,  G02B6/126

Abstract: Structures for polarization filtering and methods of forming a structure for polarization filtering. A waveguiding structure has a first waveguide core region including a first plurality of bends, a second waveguide core region including a second plurality of bends laterally spaced from the first plurality of bends by a gap, and a third waveguide core region including a third plurality of bends positioned beneath the gap. The first waveguide core region and the second waveguide core region contain a first material. The third waveguide core region contains a second material that differs in composition from the first material.

公开(公告)号：US20220262931A1

公开(公告)日：2022-08-18

申请号：US17177490

申请日：2021-02-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/06 ,  H01L29/66

Abstract: A lateral bipolar junction transistor (BJT) device includes: an emitter region, a collector region, and a base region, the base region positioned between and laterally separating the emitter region and the collector region, the base region including an intrinsic base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating a lower surface of the intrinsic base region from the semiconductor substrate.

公开(公告)号：US20220262930A1

公开(公告)日：2022-08-18

申请号：US17176251

申请日：2021-02-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Judson R. Holt ,  Tayel Nesheiwat ,  John J. Pekarik ,  Christopher Durcan

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes a substrate and a trench isolation region in the substrate. The trench isolation region surrounds an active region of the substrate. The device structure further includes a collector in the active region of the substrate, a base layer having a first section positioned on the active region and a second section oriented at an angle relative to the first section, an emitter positioned on the first section of the base layer, and an extrinsic base layer positioned over the trench isolation region and adjacent to the emitter. The second section of the base layer is laterally positioned between the extrinsic base layer and the emitter.