公开(公告)号：US20210271301A1

公开(公告)日：2021-09-02

申请号：US17141102

申请日：2021-01-04

Applicant: Rambus Inc.

Inventor： Stephen G. Tell

IPC: G06F1/26 ,  G06F13/40 ,  H04L7/02 ,  G06F1/10 ,  G06F13/38 ,  G06F12/02 ,  G11C7/10 ,  H03K19/1776

Abstract: A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.

公开(公告)号：US11108510B2

公开(公告)日：2021-08-31

申请号：US16861164

申请日：2020-04-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00 ,  H04L1/24 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C29/02 ,  G11C7/10 ,  H04L27/00 ,  G11C7/04 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US11101393B2

公开(公告)日：2021-08-24

申请号：US16673431

申请日：2019-11-04

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F13/372 ,  G06F13/16 ,  G06F12/02 ,  G06F12/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20210250038A1

公开(公告)日：2021-08-12

申请号：US17166919

申请日：2021-02-03

Applicant: Rambus Inc.

Inventor： Shankar Tangirala

IPC: H03M1/44 ,  H03M1/80

Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

公开(公告)号：US20210241822A1

公开(公告)日：2021-08-05

申请号：US16973241

申请日：2019-05-25

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C11/406

Abstract: An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.

公开(公告)号：US11082268B2

公开(公告)日：2021-08-03

申请号：US17065043

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： Robert E. Palmer

IPC: H04L25/03 ,  H04L27/01 ,  H04L7/04 ,  H04L25/06

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

公开(公告)号：US20210232507A1

公开(公告)日：2021-07-29

申请号：US17107831

申请日：2020-11-30

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/1009 ,  G06F12/0864 ,  G06F12/0811 ,  G11C7/10

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US11075671B2

公开(公告)日：2021-07-27

申请号：US16685861

申请日：2019-11-15

Applicant: Rambus Inc.

Inventor： John W. Poulton ,  Frederick A. Ware ,  Carl W. Werner

IPC: H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H03F3/24 ,  H04B3/54 ,  H04B10/50 ,  H04B10/40 ,  H04B10/073 ,  H04B1/04

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US11063741B2

公开(公告)日：2021-07-13

申请号：US16659539

申请日：2019-10-21

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared LeVan Zerbe ,  Carl William Werner

IPC: H04L7/027 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

公开(公告)号：US11062743B2

公开(公告)日：2021-07-13

申请号：US16802073

申请日：2020-02-26

Applicant: Rambus Inc.

Inventor： Michael L. Takefman ,  Maher Amer ,  Claus Reitlingshoefer ,  Riccardo Badalone

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/04

Abstract: A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.