公开(公告)号：US20020175737A1

公开(公告)日：2002-11-28

申请号：US10100510

申请日：2002-03-18

Applicant: STMicroelectronics S.A.

Inventor： Pascal Debaty

IPC: H03L005/00

CPC classification number: H03K3/356113 ,  H03K17/102

Abstract: A circuit for shifting at least one input switching signal includes a CMOS bistable circuit having two branches, and a circuit for accelerating the switching of the bistable circuit. The circuit for accelerating the switching allows an output transistor of each branch to be switched to the off state when an input transistor of the branch switches to the on state. The circuit for accelerating switching includes, for at least one given branch, an associated current mirror generating a turn-off current for the output transistor of the branch on the basis of a turn-on current for the input transistor of the branch.

Abstract translation: 用于移位至少一个输入切换信号的电路包括具有两个分支的CMOS双稳态电路和用于加速双稳态电路的切换的电路。 当分支的输入晶体管切换到导通状态时，用于加速开关的电路允许每个分支的输出晶体管切换到截止状态。 用于加速切换的电路包括对于至少一个给定的分支，相关联的电流镜根据分支的输入晶体管的导通电流为分支的输出晶体管产生截止电流。

公开(公告)号：US20020175353A1

公开(公告)日：2002-11-28

申请号：US10126442

申请日：2002-04-19

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray ,  Richard Fournel

IPC: H01L047/00 ,  H01L029/80

CPC classification number: G11C16/0433 ,  H01L27/115

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

Abstract translation: FAMOS存储器包括存储器单元，其中每个存储单元包括绝缘栅极晶体管，以及具有连接到绝缘栅极晶体管的源极的漏极的第一存取晶体管。 FAMOS存储器还包括绝缘晶体管，其具有分别连接到同一行的两个相邻单元的绝缘栅极晶体管的源极的漏极和源极。 每个绝缘栅极晶体管具有环形结构，并且梯形分离区域使得同一行的单元绝缘。

公开(公告)号：US20020174385A1

公开(公告)日：2002-11-21

申请号：US10021269

申请日：2001-12-12

Applicant: STMicroelectronics S.A.

Inventor： Andrew Cofler ,  Laurent Wojcieszak ,  Arnaud Dehamel ,  Isabelle Sename

IPC: H02H003/05

CPC classification number: G06F11/3632 ,  G06F9/30072 ,  G06F11/3648

Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.

Abstract translation: 一种用于执行具有分配的保护指示器的指令的计算机系统，包括指令提供电路，用于从供应电路接收指令的流水线执行单元以及从一组保护指示器中选择的至少一个保护指示符，所述执行单元包括主保护值存储 包括用于保护指示器的主值，以及用于解析执行流水线中的保护值的电路，以及提供用于指示流水线是否被提交到执行指令的信号的模块，以及具有用于对所选指令进行监视的监视电路的仿真器 提供给执行流水线和同步电路，用于将每个所选指令的保护指示符的分辨率与该指令的程序计数相关。

公开(公告)号：US20020167356A1

公开(公告)日：2002-11-14

申请号：US10144623

申请日：2002-05-13

Applicant: STMicroelectronics S.A.

Inventor： Claude Renous ,  Francois Van-Zanten

IPC: H03F003/45

CPC classification number: H03F3/3023 ,  H03F3/45188 ,  H03F3/45659 ,  H03F2203/45711

Abstract: A wideband differential amplifier includes a first differential stage connected to a Miller stage allowing an open-loop gain increase. The Miller stage includes a current source and a resistive-capacitive network causing a feedback into the current source. The feedback includes a portion of a Miller stage output signal having a high frequency range to move a bias point of the current source within the high frequency range. Thus, a gain of the Miller stage significantly increases towards the bias point.

Abstract translation: 宽带差分放大器包括连接到Miller级的第一差分级，允许开环增益增加。 米勒级包括电流源和电阻电容网络，导致反馈到电流源。 反馈包括具有高频范围的米勒级输出信号的一部分，以将电流源的偏置点移动到高频范围内。 因此，米勒阶段的增益显着地朝向偏向点增加。

公开(公告)号：US20020162677A1

公开(公告)日：2002-11-07

申请号：US10136682

申请日：2002-05-01

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Christian Caillat

IPC: H02G003/08

CPC classification number: H01L28/40 ,  H01L21/3144 ,  H01L23/5223 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated component, in which process and component a first electrode is in the form of a cup; a layer made of a dielectric covers at least the wall of the first electrode; a second electrode fills the cup; a first electrical connection via lies above the second electrode; and a second electrical connection via lies laterally with respect to and at a predetermined distance from the first electrode and is connected to the first electrode.

Abstract translation: 用于制造组件的方法，例如集成电路中的电容器和集成部件，其中第一电极是杯形式的工艺和部件; 由电介质覆盖的层至少覆盖第一电极的壁; 第二电极填充杯子; 第一电连接通孔位于第二电极上方; 并且第二电连接通孔相对于第一电极相对于并且距离第一电极具有预定距离横向延伸并且连接到第一电极。

公开(公告)号：US20020147901A1

公开(公告)日：2002-10-10

申请号：US10083629

申请日：2002-02-26

Applicant: STMicroelectronics S.A.

Inventor： Andrew Cofler

IPC: G06F009/00

CPC classification number: G06F9/3814 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3889

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

Abstract translation: 处理单元与第一FIFO型存储器和第二FIFO型存储器相关联。 用于将存储器存储的数据加载到处理单元内的寄存器的每个指令被存储在第一FIFO型存储器中，并且其它操作指令被存储在第二FIFO型存储器中。 如果在第一FIFO型存储器中不存在用于修改与该操作指令相关联的寄存器的值的时间上的加载指令，则从第二FIFO型存储器移除涉及寄存器的操作指令。 在存在这种较早的加载指令的情况下，仅在从第一FIFO型存储器移除了加载指令之后，将操作指令从第二FIFO型存储器中移除。

公开(公告)号：US20020145446A1

公开(公告)日：2002-10-10

申请号：US10073680

申请日：2002-02-11

Applicant: STMicroelectronics S.A.

Inventor： Leila Aitouarab

IPC: H03K019/094

CPC classification number: H03K17/693 ,  H03K3/356147 ,  H03K17/102

Abstract: A voltage-switching device includes a high-voltage translator connected to a high-voltage node receiving either a low-voltage logic level or a high-voltage level as a function of a low-voltage/high-voltage mode control signal to provide at least one output signal as a function of this mode control signal and of a switching control signal. A voltage-level switching circuit is controlled by output signals from the high-voltage translator and by the mode control signal and the switching control signal for application, as output voltage levels, of either ground or the low-voltage logic level in low-voltage mode or the high-voltage level in high-voltage mode.

Abstract translation: 电压切换装置包括连接到接收低电压逻辑电平或高电压电平的高压节点的高压转换器，作为低电压/高电压模式控制信号的函数，以提供 作为该模式控制信号和切换控制信号的函数的至少一个输出信号。 电压电平开关电路由来自高电压转换器的输出信号和模拟控制信号和用于施加的开关控制信号控制，作为低电压的接地或低电压逻辑电平的输出电压电平 模式或高电压电平。

公开(公告)号：US20020135379A1

公开(公告)日：2002-09-26

申请号：US10060105

申请日：2002-01-29

Applicant: STMicroelectronics S.A.

Inventor： Christophe Moreaux ,  Ahmed Kari

IPC: G01R031/00

CPC classification number: G01R31/043

Abstract: A device for detecting a defective power supply connection in an integrated circuit includes a comparison circuit for comparing voltage levels of an input/output pad of the integrated circuit and an internal power supply line connected to a power supply pad of the integrated circuit. A pull-down or pull-up device is connected between the input/output pad and the internal power supply line.

Abstract translation: 用于检测集成电路中的有缺陷的电源连接的装置包括比较电路，用于比较集成电路的输入/输出焊盘的电压电平和连接到集成电路的电源焊盘的内部电源线。 在输入/输出板和内部电源线之间连接一个下拉或上拉设备。

公开(公告)号：US20020135020A1

公开(公告)日：2002-09-26

申请号：US10084255

申请日：2002-02-27

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Alexandre Villaret

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76289 ,  H01L29/66772

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract translation: 源极，漏极和沟道区域通过绝缘层在垂直于载体衬底完全隔离的硅层中产生，并且通过浅沟槽类型的横向隔离区域横向限定。

公开(公告)号：US20020129219A1

公开(公告)日：2002-09-12

申请号：US10081740

申请日：2002-02-22

Applicant: STMicroelectronics S.A.

Inventor： Yvon Bahout

IPC: G06F012/02

CPC classification number: G11C8/04

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract translation: 依次读取实现增量地址计数器的存储器。 地址跳转包括检测地址跳转信号，递增增量地址计数器以及以递增的地址读取存储器的内容。 在增量地址读取的内容被传送到增量地址计数器，并且在包含在增量地址计数器中的地址读取存储器的内容。