公开(公告)号：US20140206154A1

公开(公告)日：2014-07-24

申请号：US14221921

申请日：2014-03-21

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Romain Coffy ,  Yvon Imbs ,  Laurent Marechal

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/185 ,  H05K2201/10015 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Abstract translation: 半导体器件包括具有前侧和后侧的晶片。 晶片由至少一个集成电路芯片形成，该集成电路芯片具有与晶片前侧共面的电连接，以及与晶片背面共面的背面。 包括至少一个导电板和电介质板的无源部件位于集成电路芯片附近。 封装块嵌入集成电路芯片和无源部件，该块具有与晶片前侧共面的前侧和与晶片背面共面的背面。 在电连接前端和被动部件之间进行电连接。 该电连接包括放置在晶片正面和晶片背面上的连接线。 电连接还包括至少一个通过封装块的通孔。

公开(公告)号：US20130248887A1

公开(公告)日：2013-09-26

申请号：US13845445

申请日：2013-03-18

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS PTE LTD

Inventor： Romain Coffy ,  Eric Saugier ,  Hk Looi ,  Norbert Chevrier

IPC: H01L31/0203 ,  H01L31/18

CPC classification number: H01L31/0203 ,  G01S7/481 ,  G01S17/026 ,  H01L25/167 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/181 ,  H03K17/941 ,  H03K2017/9455 ,  H03K2217/94026 ,  H03K2217/94112 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.

Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。

公开(公告)号：US12285534B2

公开(公告)日：2025-04-29

申请号：US17328435

申请日：2021-05-24

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Roberto La Rosa ,  Jean Camiolo ,  Laurent Yvan Louis Jamet

IPC: A61L2/24 ,  A61L2/10 ,  G08C17/02 ,  G08B7/06

Abstract: A system to sanitize a surface includes an emitter. The emitter of the system to sanitize the surface includes: a light source configured to generate light at a sanitizing wavelength; a receiver configured to receive a wireless signal; and a processing circuit for the emitter configured to turn the light source on, turn the light source off, and adjust an intensity of light generated by the light source depending on the wireless signal. The system to sanitize the surface further includes a sensor. The sensor of the system to sanitize the surface includes: a photoelectric transducer configured to convert light at the sanitizing wavelength to a current; and a processing circuit for the sensor powered by the current and in communication with a transmitter to transmit the wireless signal, the processing circuit for the sensor being configured to control emission of the wireless signal depending on a power level supplied by the current.

公开(公告)号：US12274003B2

公开(公告)日：2025-04-08

申请号：US17961911

申请日：2022-10-07

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Patrick Laurent ,  Jean-Michel Riviere

IPC: H05K1/02 ,  B81B7/02 ,  H01L23/13 ,  H01L23/24 ,  H01L23/552 ,  H01L23/66 ,  H04R19/04 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  G01S7/481

Abstract: A device includes comprising first and second printed circuit boards. Walls couple the first and second printed circuit boards to each other and define a first cavity between the first and second printed circuit boards. Electric conductors associated with the walls electrically connect the first and second printed circuit boards. An integrated circuit chip is mounted to a first surface of the first integrated circuit board in the first cavity. The integrated circuit chip is electrically connected to conductive tracks of the first surface of the first printed circuit board. Surface-mounted components are mounted on top of and in contact with conductive tracks of a first surface of the second printed circuit board. The first surfaces of the first and second printed circuit boards are arranged facing towards each other. The first and second printed circuit boards may form rigid components of a flex-rigid type printed circuit board.

公开(公告)号：US20250103127A1

公开(公告)日：2025-03-27

申请号：US18832431

申请日：2023-01-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Philippe Isola ,  Olivier Sauvage

IPC: G06F1/3234

Abstract: An example computer system includes at least two processors, a power supply controller, configuration registers, and a wake-up circuit. The computer system has a deep sleep mode in which the processors are not supplied with power. The power supply controller is configured to detect events of different types to be processed in the processors in the deep sleep mode. The configuration registers are configured to assign the processing to the different processors according to the type of event detected. The wake-up circuit is configured to disable deep sleep mode after an event is detected, and activate, when disabling deep sleep mode, a power supply of one of the at least two processor to which the processing of the detected event has been assigned according to the configuration registers. The activation of the power supply powering on one of the processors, which is configured to process the detected event.

公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20250055492A1

公开(公告)日：2025-02-13

申请号：US18929262

申请日：2024-10-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Danika Perrin ,  Sandrine Nicolas

IPC: H04B1/16

Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

公开(公告)号：US12212866B2

公开(公告)日：2025-01-28

申请号：US18500449

申请日：2023-11-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Simony

IPC: H04N25/709 ,  G05F1/575 ,  G05F3/20 ,  H02M1/00 ,  H02M1/088 ,  H02M3/155 ,  H04N25/77

Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.

公开(公告)号：US12174950B2

公开(公告)日：2024-12-24

申请号：US17644711

申请日：2021-12-16

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Diana Moisuc ,  Christophe Eichwald

IPC: G06F21/55 ,  G06F3/06 ,  G06F9/30

Abstract: Method for detecting the linear extraction of information in a processor using an instruction pointer. The method includes monitoring the values of the instruction pointer, determining a number of consecutive increments incrementing the values of the instruction pointer by a constant amount, and generating a detection signal if the number is greater than or equal to a detection threshold.

公开(公告)号：US12149250B2

公开(公告)日：2024-11-19

申请号：US17412991

申请日：2021-08-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Denis Cottin ,  Fabrice Romain

IPC: H03K3/356 ,  G09G3/3225 ,  H03K19/0185

Abstract: An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.