公开(公告)号：US12162134B2

公开(公告)日：2024-12-10

申请号：US18170962

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Ti Wang ,  Chih-Wei Lin ,  Fu-Hsien Li ,  Yi-Ming Chen ,  Cheng-Ho Hung

IPC: B25J11/00 ,  B23P6/00 ,  B25J1/04 ,  B25J18/00 ,  G01B11/24 ,  G01B11/30 ,  G01N33/00 ,  H01L21/02 ,  H01L21/66 ,  H01L21/673 ,  H01L21/677

Abstract: A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.

公开(公告)号：US20240405100A1

公开(公告)日：2024-12-05

申请号：US18482758

申请日：2023-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Sheng TANG ,  Chen-Yen KAO ,  Jheng-Syun YANG

IPC: H01L29/66 ,  G03F7/00 ,  H01L21/8234 ,  H01L23/544 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: An integrated circuit includes a device region and an overlay mark region. The device region includes a plurality of stacked channels of a transistor, a source/drain region of the transistor, a source/drain contact of a first material on the source/drain region, and a conductive via of a second material in contact with the source/drain contact. The overlay mark region includes a first diffraction grating of first metal structures of the first material and a second first diffraction grating of second metal structures above of the second material above and offset from the first metal structures.

公开(公告)号：US20240405021A1

公开(公告)日：2024-12-05

申请号：US18468409

申请日：2023-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Chia-Hao Chang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A device includes first nanostructures over a substrate; second nanostructures over the substrate, wherein the first nanostructures are laterally separated from the second nanostructures by an isolation structure between the first nanostructures and the second nanostructures; a first gate structure around each first nanostructure and around each second nanostructure, wherein the first gate structure extends over the isolation structure; third nanostructures over the substrate; and a second gate structure around each third nanostructure, wherein the second gate structure is separated from the first gate structure by a dielectric wall.

公开(公告)号：US20240404885A1

公开(公告)日：2024-12-05

申请号：US18782214

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin.

公开(公告)号：US20240404857A1

公开(公告)日：2024-12-05

申请号：US18412310

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hao LIAO ,  Pei-Yu LEE ,  Chih-Tsung LEE ,  Cheng-Lung WU ,  Jiun-Rong PAI

IPC: H01L21/677 ,  H01L21/324 ,  H01L21/673

Abstract: Base plates of a substrate retainer transportation mechanism are provided with damping members to assist elastic members in damping and limiting movement of the substrate retainer transportation mechanism when the substrate transportation mechanism is subjected to unwanted external forces, e.g., seismic forces. By damping and limiting movement of the substrate retainer transportation mechanism, undesirable damage to substrates contained in a substrate retainer being carried by the substrate retainer transport mechanism can be minimized.

公开(公告)号：US12160998B2

公开(公告)日：2024-12-03

申请号：US17871676

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Zong-You Luo ,  Ya-Jui Tsou ,  I-Cheng Tung ,  CheeWee Liu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

公开(公告)号：US12160985B2

公开(公告)日：2024-12-03

申请号：US18151991

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: G11C11/41 ,  G11C11/418 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US12159860B2

公开(公告)日：2024-12-03

申请号：US17833100

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L21/768

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

公开(公告)号：US12159830B2

公开(公告)日：2024-12-03

申请号：US18068615

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Lee ,  Po-Hsiang Huang ,  Wen-Sheh Huang ,  Jen Hung Wang ,  Su-Jen Sung ,  Chih-Chien Chi ,  Pei-Hsuan Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

公开(公告)号：US12159822B2

公开(公告)日：2024-12-03

申请号：US17805594

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.