公开(公告)号：US20200279768A1

公开(公告)日：2020-09-03

申请号：US16290178

申请日：2019-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Ruilong Xie ,  Kangguo Cheng ,  Adra V. Carr

IPC: H01L21/768 ,  H01L23/532

Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US10734499B2

公开(公告)日：2020-08-04

申请号：US15986031

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

公开(公告)号：US10727308B2

公开(公告)日：2020-07-28

申请号：US16548335

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.

公开(公告)号：US10727136B2

公开(公告)日：2020-07-28

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US10720391B1

公开(公告)日：2020-07-21

申请号：US16240335

申请日：2019-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Lars W. Liebmann ,  Ruilong Xie

IPC: H01L23/00 ,  H01L23/535 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L27/11 ,  H01L21/02 ,  H01L29/66

Abstract: A method of forming a buried local interconnect is disclosed including, among other things, forming a first sacrificial layer embedded between a first semiconductor layer and a second semiconductor layer, forming a plurality of fin structures above the second semiconductor layer, forming a mask layer having an opening positioned between an adjacent pair of the fin structures, removing a portion of the second semiconductor layer exposed by the opening to expose the first sacrificial layer and define a first cavity in the second semiconductor layer, removing portions of the first sacrificial layer positioned between the first semiconductor layer and the second semiconductor layer to form lateral cavity extensions of the first cavity, forming a first liner layer in the first cavity, and forming a conductive interconnect in the first cavity over the first liner layer.

公开(公告)号：US10707218B2

公开(公告)日：2020-07-07

申请号：US16045920

申请日：2018-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie

IPC: H01L27/11 ,  H01L27/12 ,  G11C11/412 ,  H01L29/06

Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.

公开(公告)号：US10699957B2

公开(公告)日：2020-06-30

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3105

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US20200168509A1

公开(公告)日：2020-05-28

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US20200161190A1

公开(公告)日：2020-05-21

申请号：US16196413

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/762

Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.