公开(公告)号：US20130221446A1

公开(公告)日：2013-08-29

申请号：US13850840

申请日：2013-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/498 ,  H01L29/78

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20250096202A1

公开(公告)日：2025-03-20

申请号：US18788541

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Wei Zhou

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. A first dielectric material is disposed around the first plurality of stacked memory dies. A second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. A third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.

公开(公告)号：US20250096171A1

公开(公告)日：2025-03-20

申请号：US18789049

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/683 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H10B80/00

Abstract: A method of forming a semiconductor wafer is provided. The method includes dicing wafers into dies, testing the dies for known good dies, and bonding known good dies to a carrier wafer to form a top KGD wafer. The method also includes filling gaps between top dies to form a top gap-fill layer around and above each of the top dies, and bonding the top dies with a dummy silicon wafer. The method also includes bonding known good dies to carrier wafers to form one or more core KGD wafers, as well as filling gaps between the core dies to form a core gap-fill layer around each of the core dies. The method then includes bonding the one or more core KGD wafers to the top KGD wafer to form a KGD wafer stack.

公开(公告)号：US20250079366A1

公开(公告)日：2025-03-06

申请号：US18788588

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Bharat Bhushan

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor device assembly with layered dielectric is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. The second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. The tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). In contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). As a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.

公开(公告)号：US12243610B2

公开(公告)日：2025-03-04

申请号：US17821676

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/56

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

公开(公告)号：US12205865B2

公开(公告)日：2025-01-21

申请号：US17720238

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Angela S. Parekh

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface completely through a body of the monolithic silicon structure to a top surface of the monolithic silicon structure; and a second semiconductor device disposed in the cavity, the second semiconductor device including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

公开(公告)号：US12185537B2

公开(公告)日：2024-12-31

申请号：US17378743

申请日：2021-07-18

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L21/00 ,  H01L21/338 ,  H01L27/115 ,  H01L29/66 ,  H01L29/74 ,  H01L29/78 ,  H01L29/80 ,  H10B43/27 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US12183716B2

公开(公告)日：2024-12-31

申请号：US17711583

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K Street ,  Kunal R. Parekh

IPC: H01L25/00 ,  H01L25/065

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

公开(公告)号：US20240421030A1

公开(公告)日：2024-12-19

申请号：US18674664

申请日：2024-05-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Amy R. Griffin ,  Kunal R. Parekh ,  Akshay N. Singh

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor device is provided. The semiconductor device includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die at a first location above a back side surface of the logic die, a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the back side surface of logic die, a first dielectric material disposed above the back side surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality and second plurality of stacked memory dies through a second dielectric layer having dielectric-dielectric fusion bonding.

公开(公告)号：US20240413145A1

公开(公告)日：2024-12-12

申请号：US18808990

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.