公开(公告)号：US10068982B2

公开(公告)日：2018-09-04

申请号：US14290569

申请日：2014-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Tung-Wen Cheng ,  Mu-Tsang Lin

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L27/092

Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure also includes a dielectric structure over the semiconductor substrate and adjacent to the gate stack. The dielectric structure is in direct contact with the work function layer and the metal filling.

公开(公告)号：US10032916B2

公开(公告)日：2018-07-24

申请号：US15467643

申请日：2017-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and partially removing the spacer elements such that an upper portion of the recess becomes wider. The method further includes forming a metal gate stack in the recess and forming a protection element in the recess to cover the metal gate stack.

公开(公告)号：US09997632B2

公开(公告)日：2018-06-12

申请号：US14968910

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/7856 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02631 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76841 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin-type field effect transistor device including a substrate, at least one gate stack structure, spacers and source and drain regions is described. The gate stack structure is disposed on the substrate and the spacers are disposed on sidewalls of the gate stack structure. The source and drain regions are disposed in the substrate and located at opposite sides of the gate stack structures. A dielectric layer having contact openings is disposed over the substrate and covers the gate stack structures. Metal connectors are disposed within the contact openings and connected to the source and drain regions, and adhesion layers are sandwiched between the contact openings and the metal connectors located within the contact openings.

公开(公告)号：US09985031B2

公开(公告)日：2018-05-29

申请号：US15074985

申请日：2016-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/3215

CPC classification number: H01L27/0924 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/4238 ,  H01L29/66545

Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

公开(公告)号：US09954081B2

公开(公告)日：2018-04-24

申请号：US14968916

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is conformally formed to cover the sidewalls of the spacers, the exposed portion of the semiconductor fin and the exposed portions of the insulators, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed on the second dielectric layer and between the spacers.

公开(公告)号：US09892957B2

公开(公告)日：2018-02-13

申请号：US14659170

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Wei-Ting Chen ,  Che-Cheng Chang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.

公开(公告)号：US09887136B2

公开(公告)日：2018-02-06

申请号：US15473627

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/66545

Abstract: Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first region, and a first end sidewall of the first gate is faced to a second end sidewall of the second gate. Third and fourth gates are on the substrate in the second region, and a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate. A dielectric layer is between the first and second gates and between the third and fourth gates. The first and second regions have different pattern densities, and an included angle between the substrate and a sidewall of the dielectric layer between the first and second gates is different from an included angle between the substrate and a sidewall of the dielectric layer between the third and fourth gates.

公开(公告)号：US20180019240A1

公开(公告)日：2018-01-18

申请号：US15706764

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

公开(公告)号：US20170358678A1

公开(公告)日：2017-12-14

申请号：US15665395

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US09799771B2

公开(公告)日：2017-10-24

申请号：US14690720

申请日：2015-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Wen Cheng ,  Che-Cheng Chang ,  Mu-Tsang Lin ,  Zhe-Hao Zhang

IPC: H01L29/78 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7853 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods for manufacturing a FinFET and a FinFET are provided. In various embodiments, the method for manufacturing a FinFET includes etching a base substrate to form a trapezoidal fin structure. Next, an isolation layer is deposited covering the etched base substrate. Then, the trapezoidal fin structure is exposed. The trapezoidal fin structure includes a top surface and a bottom surface, and the top surface has a width larger than that of the bottom surface.